Class D Audio Amplifier IC Forum Discussions
I've been assigned with debugging an existing 4-channel class-d amplifier based on IRS2093. Details and questions below. My idea was to put all questions in one post but if this is not desired then just let me know.
Details for the current design:
Class-D Driver: IRS2093MPbF
MOSFET: IRFB5615 (one pair per channel)
Fsw: 380 KHz
Dead-time: 105 ns.
Gate stoppers: 10 Ohm
Rail voltage: just under 100V (2 x 48,5V)
One of the first things I noticed is that the IRS2093 runs quite hot, too hot for my taste.
I did not do extensive testing but a quick test with opened case @ room temperature (much better cooling than worst case) gave me around 90 degrees celcius on the FLIR on the IRS2093. If I take into account the the unit will be running with the lid closed and the heatsink reaching > 70 degrees in worst case conditions then my best guess is that the IC is running too hot.
I wanted to get a better picture of the power dissipation in our design, so I decided to check the math as described in Application Note AN-1146 - Junction Temperature Estimation. I got stuck on:
7.4 PLSH: Power Dissipation of the High-side Level Shifter
PLSH = 0.4nC x fsw x VBUS x 4
All is clear except "nC". What is nC supposed to be?
I suspected the Mosfet Gate charge but that doesn't make sense as in the rest of the calculations, the gate charge is refered to as Qg.
Anyway, in order to cool down the IC, my idea was to:
- reduce Vcc from 15V to 12V. Sounds good?
- if that is not enough, reduce Fsw and/or rail voltage, find compromise between performance and reliability.
The IRFB5615 have a gate charge of 27nc, seems like this should not pose a major issue for this IC?
The Application Note AN-1146 shows a nice table for setting Fsw, assuming a feedback resistor of 47k.
The design I'm working on seems to be loosely based on IRAUDAMP8 which uses Rfb = 100k.
Not sure why the AN says to use 47k and IRAUDAMP8 uses 100k? There's not a lot of info to work with here so I guessed I'd better ask.
DT is set to the highest value (105ns) which seems like quite a lot to me for IRFB5615 but I have yet to check double check if it can be reduced. My guess is that if it can be reduced, THD will drop but it won't solve the issue of the IRS2093 running so hot?
I checked the THD and that seams to be OK (all things considering), the lowest being around 0,02% @ 50W.
The amplifier was designed to do 4 x 200W @ 4 ohm or 4 x 300W @ 2 Ohm <= 1% THD, 1 KHz and in fact it does (at least for a short period). My guess is that if we run 2 channels on 4 Ohm and two channels on 2 ohm, the 2 Ohm power rating will go up considerably, well exceeding 300W per channel which seems a bit much to me? Maybe pushing the limits of these devices?
Over Current Protection
OCP is disabled in the current design and I would rather enable it if possible. However the Application note says:
2. Switching Speed
Internal over current protection has a certain time window to measure the output current. If switching
transition takes too long, the internal OCP circuitry starts monitoring voltage across the MOSFET which
induces false triggering of OCP. Less than 20nC of gate charge per output is recommended.
The IRFB5615 have a gate charge of 27nc so we can't (or shouldn't) enable OCP?
The word "recommended" leaves room for interpretation.
Final note: Please note that this is not my design and that I'm quite new to class-d amplifier design. Just trying to learn and improve the existing design. So if you have any additional suggestions I'd be more than welcome to hear them.
Hello! , I used arduino to try to set the value of Select Power Mode Profile setting, using I2c.write(0x20, 0x00, 0x01); Successful, but all the settings are restored after the power is cut off, can I not permanently write the configuration settings of the MA12070?
1.Both AD0 and AD1 are grounded
On the Datasheet for the MA12040P Amp IC, pins 49 and 64 are designated as do not connect, as they are internally connected to 5V -- however, on the MA12040P Amp Eval board (and documented on the eval board schematic) these pins are externally connected to 5V.
We've got jumpers on our board so we can connect to 5V or not --
Can you provide guidance here? Why is the eval board connecting these pins to external 5V, despite the Datasheet guidance?
With respect to Infineon's Class D Audio Amp, P/N IRFB4020PBF, the datasheet states, "Can deliver up to 300W per channel into 8 (ohm) load in half-bridge configuration".
What is this 300 Watt limit based on?
What are the test conditions?
Assuming the thermal design is okay, can it allow for more power and current than limited by this statement?
Reference datasheet linked @ https://www.infineon.com/cms/en/product/power/mosfet/n-channel/irfb4020/
Is there any internal difference in the chip with CREF PIN 20 vs AVSS PIN 20?
I have developed a custom PCB using the IRS2452AM Class D audio amplifier control IC and came across an issue I need help with. For my specific problem I need to switch at a minimum of 500kHz (although I have seen this same issue no matter what switching frequency I use) and I noticed that at idle (Zero Volt Switching "ZVS") I was developing a DC bias on my output. I tracked this back to an uneven duty cycle between the positive and negative halves of the bridge. Looking into it further I realized that my high side FETs are not turning off when they should and are staying on too long. There is even SHOOT THROUGH during every transition. Initially I thought the issue was just on my PCB, however after getting out the IRAUDAMP23 I have found the same issue there.
It looks like there is a delay between when the IC is trying to pull down the drive signal (HO1 and HO2) and the FET actually turning off. This delay is constant no matter the frequency, but with higher switching frequencies it becomes more apparent and results in the uneven switching I am seeing.
Since I am switching at a high rate I implemented the optional gate driver circuits laid out in AN_1811_PL88_1811_234119 "IRS2452AM Class D Amplifier IC Functional Description" and also used in the IRAUDAMP23 Development kit datasheet (of which I have one)
The scope screen grabs below are pulled from the IRAUDAMP23 dev board.
This first image is of the HO1 signal attempting to drive the high side FET. Notice the stair step on the turn ON and the delay in the turn off.
This second image is of the turn OFF for HO1 (Yellow) and the turn on for LO1 (Blue). Notice that if HO1 had turned off when it first tried to there would have been ~40ns of deadtime which matches my settings. Instead there is about 40ns of Shoot Through!
Here there is the turn off for the Gate on the High Side FET (BLUE) and the turn on for the low side FET (Yellow). Note Shoot Through causing the gate on the Low side FET (Yellow) To be sagged down significantly.
Is this a known issue with high side of the gate drive circuit called out in the app note or an issue with the IC?
I would really like to not have shoot through.Show Less
I am attempting to use the IRS2452AM Class D amplifier in the Full Bridge (BTL Mode) configuration to drive a step up transformer. Right now I am using the IRAUDAMP23 development kit to verify my design before laying out custom hardware. My current issue is that when I turn on the chip (i.e. when I flip the reset switch on the dev board to enable the chip) the device does not do any switching if a load is connected. If I disconnect the load, the device immediately starts switching as I would expect a full bridge amplifier to do so. In some cases I can re-connect the load and device continues switching and pushing power out to the load, in others it stops switching again.
Right now I'm driving the bridge outputs directly into a resistor. I'm using +-20v for supply and have used a 4k and 180 ohm power resistors as load.
At first I was suspicious of OCP (over current protection) triggering, but I see no evidence of that when I monitor the CSD pin.
If I run the IC in half bridge mode it always works when I switch it on.