Class D Audio Amplifier IC Forum Discussions
Hello;
In this PP sate they are facing problem in 1 set that IRS2093 PWM driver outputted noise at low side PWM driver LO1 (pin15).
This noise appears after 1m from set power ON without input or load.
Please refer to attached file for more detail and the schematic diagram.
please advise.
Thank you
Zhang Di
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Good day!
Now i'm designing 30W * 2ch audio AMP with IRS2093MPbF.
Could you please tell me termination of un-used pin (=IN, COMP, VB, VS, HO, LO, CSH of CH 3/4)?
ex) COMPn should be connect the same net as GND, etc.
And also please tell me what will happen those pins are open.
#I could not find it on datasheet or apprication note.
It is OK that un-used output pin should be open,right?
Show LessDear Infineon community,
I get a pop/click noise every time I change the input audio sampling rates, I tried to pull NMUTE pin low at the same time but makes no help. I2S clock will missing for a while when sampling rates change and causes pll fault.
Is there a way to avoid pop noise? How should I handle the timing of signals. By the way, the audio sources from PC, so I don't have many ways to control the I2S signal.
Thank you very much!
FireRunning
Show LessDoes anyone have GUI software to change PMP5 registers?
BR
Toshinari Ikeuchi/TED
Hello!
I'm writing to you to ask about possibility to add additional export file format for DSP in next SW releases.
By creating project we have AMP config and DSP as .csv files. It will be great to have possibility to export DSP parameters in more friendly format for EEPROMs - for example - Intel HEX. In this case users can very easly create own designs where low cost uC is in use.
Thank you very much!
Przemek
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Hello...
We are using IRS2452AM in 200W power amplifier application. 3 IC's are used in one PCB to make 6 independent power amplifier in 1 board. All the 6 half bridges are using common high voltage sources of +/-150V. When 1 power amplifier channel of any IC fails in the board all the 3 IC's and 12 MOSFET's are failing even when the remaining power amplifier channels are not given sine wave input. I would like to know if there is any data on IC that can justify this failure.
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We are currently experiencing a high failure rate among the MA12040 amp ics used in the following circuit:
We are currently configured for a full bridge tied load (R45 and R44 are populated and L3 and L4 are not) - all output is going to J8. PVDD is between 12V and 18V.
This design is producing subjectively good audio output results - but it seems highly sensitive to electrical failure. We're seeing amp ics fail from time to time with no obvious cause. There have been a couple which failed due to shorts between a pair of adjacent capacitors (C42 - C46) -- but even when no obvious stress occurred we're getting a number of failures with similar outcomes (IC internally shorted).
A couple questions: is there anything about this design that could explain this sensitivity - and/or should be remedied to improve performance? Is there anything about the new MA12070 amp IC that will improve this issue?
Thanks very much for any insights / input.
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I've been assigned with debugging an existing 4-channel class-d amplifier based on IRS2093. Details and questions below. My idea was to put all questions in one post but if this is not desired then just let me know.
Details for the current design:
Class-D Driver: IRS2093MPbF
MOSFET: IRFB5615 (one pair per channel)
Topology: half-bridge
Fsw: 380 KHz
Dead-time: 105 ns.
Vcc: 15V
Gate stoppers: 10 Ohm
Rail voltage: just under 100V (2 x 48,5V)
Junction temperature
One of the first things I noticed is that the IRS2093 runs quite hot, too hot for my taste.
I did not do extensive testing but a quick test with opened case @ room temperature (much better cooling than worst case) gave me around 90 degrees celcius on the FLIR on the IRS2093. If I take into account the the unit will be running with the lid closed and the heatsink reaching > 70 degrees in worst case conditions then my best guess is that the IC is running too hot.
I wanted to get a better picture of the power dissipation in our design, so I decided to check the math as described in Application Note AN-1146 - Junction Temperature Estimation. I got stuck on:
7.4 PLSH: Power Dissipation of the High-side Level Shifter
PLSH = 0.4nC x fsw x VBUS x 4
All is clear except "nC". What is nC supposed to be?
I suspected the Mosfet Gate charge but that doesn't make sense as in the rest of the calculations, the gate charge is refered to as Qg.
Anyway, in order to cool down the IC, my idea was to:
- reduce Vcc from 15V to 12V. Sounds good?
- if that is not enough, reduce Fsw and/or rail voltage, find compromise between performance and reliability.
The IRFB5615 have a gate charge of 27nc, seems like this should not pose a major issue for this IC?
Feedback resistor.
The Application Note AN-1146 shows a nice table for setting Fsw, assuming a feedback resistor of 47k.
The design I'm working on seems to be loosely based on IRAUDAMP8 which uses Rfb = 100k.
Not sure why the AN says to use 47k and IRAUDAMP8 uses 100k? There's not a lot of info to work with here so I guessed I'd better ask.
Dead-time
DT is set to the highest value (105ns) which seems like quite a lot to me for IRFB5615 but I have yet to check double check if it can be reduced. My guess is that if it can be reduced, THD will drop but it won't solve the issue of the IRS2093 running so hot?
I checked the THD and that seams to be OK (all things considering), the lowest being around 0,02% @ 50W.
Output power
The amplifier was designed to do 4 x 200W @ 4 ohm or 4 x 300W @ 2 Ohm <= 1% THD, 1 KHz and in fact it does (at least for a short period). My guess is that if we run 2 channels on 4 Ohm and two channels on 2 ohm, the 2 Ohm power rating will go up considerably, well exceeding 300W per channel which seems a bit much to me? Maybe pushing the limits of these devices?
Over Current Protection
OCP is disabled in the current design and I would rather enable it if possible. However the Application note says:
2. Switching Speed
Internal over current protection has a certain time window to measure the output current. If switching
transition takes too long, the internal OCP circuitry starts monitoring voltage across the MOSFET which
induces false triggering of OCP. Less than 20nC of gate charge per output is recommended.
The IRFB5615 have a gate charge of 27nc so we can't (or shouldn't) enable OCP?
The word "recommended" leaves room for interpretation.
Final note: Please note that this is not my design and that I'm quite new to class-d amplifier design. Just trying to learn and improve the existing design. So if you have any additional suggestions I'd be more than welcome to hear them.
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Dear Developer team / community
we are looking to make a design for audio amplifier , our target is to achieve 3000W /ch
2 ch amp we are planning to make.
3000W/CH at 4 ohm load we are planning.
can u please suggest the CHIPSET we should use, and some application notes /document on this.
rgds
yogesh singhal
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could you please answer the following question we received via social media? Here is the link to our post: https://www.facebook.com/345383962211058/posts/5944904058925659/
‘’What's the technology? Is it still MOSFET, or is it GaN or a hybrid?’’
Thank you very much.
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