Kindly help me with the following questions:
1. What should be the preferred voltage on MSEL0, MSEL1, nMUTE, nENABLE, nClip, nERROR, SCL, SDA, CLKM/S, CLKIO, AD0 and AD1? 3.3V or 5V?
2. What would be preferred way to generate VDD: 1. From PVDD using a linear regulator or 2. From an isolated supply? If using VDD from an isolated supply is preferred, what would be an ideal place to tie the two grounds together?
3. If using an isolated supply is preferred, I am assuming that AVSS, DVSS, CREF and CDC should be tied to the isolated ground. Is my assumption correct?
Thanks in advance!
I am confused. I understand that PVDD = 24V.
As per your reply, MSEL0, MSEL1, nMUTE, nENABLE, nClip, nERROR, SCL, SDA, CLKM/S, CLKIO, AD0 and AD1 should be 3.3V.
So now should VDD also be 3.3V or should it be 5V. If it needs to be 5V then the IC will need three supplies: 24V, 5V and 3.3V and that is not very elegant.
If the IC needs 5V for VDD, does it, using an internal regulator, convert it to 3.3V? Say at CRef (pin-20)? If yes, can we use it to pull-up the IO pins as needed?
Unless a complete reference application circuit incorporating all the design details is not published soon, I will not have full confidence to freeze my design and start layout.
Thank you for your early reply and for the link to the document.
Here is where things could be going wrong: The document which you referred to is v1.1 dt. Dec. 18, 2018, updated on the website on Feb. 5, 2019.
Kindly take a look at the document here. I referred to this document as I thought this had the latest date and so would me most updated. It is dated Apr. 28, 2019 and updated on the website on Mar. 23, 2022.
I expected this document to incorporate the hardware changes in the ERRATA dated. Apr. 8, 2019 and published on the website on Feb. 11, 2022. Unfortunately, it lacks both mention of use of clamping diodes on output pins and use of 3.3V supply
You can use 5V for everything except for the I2C pull ups, which require 3.3V logic. In the reference design or in the evaluation board this is the same case. However, in the evaluation board we generate pull ups on board but not in the reference design. Below are the logic levels of each pins for their high and low spec:
Regarding the errata sheet, some of its items are not implemented as they are valid for specific conditions. However, they are being implemented in a new evaluation board that will be public soon.