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Class D Audio Amplifier IC Forum Discussions

Audio-guru-CPH
Employee
5 solutions authored 25 sign-ins 10 replies posted
Employee

We built a design with MA12070 but it does not start up.

I tried to find hints in data sheet, but little is given regarding required voltage levels (or impedance) at input pins to stimulate operation.

CLKM is connected to 5V over 10k resistor.

Is there a need to program MA12070 samples before use or are they delivered to start already without any controller ever connected?

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1 Solution
Audio-guru-CPH
Employee
5 solutions authored 25 sign-ins 10 replies posted
Employee

Using 10kohm resistors for pull-up on I/O pins should work perfectly fine, but can be omitted by directly hardwiring to +5V. No series resistor is need. The input impedance of the I/O pins are very high.

The MA12070 should power up without any programming/controller. ENABLE pin should be tied low and MUTE brought up slowly by an RC network, ensuring no click/pops when starting up.

This is done correctly by R3/C24 in the schematic.

The device should be in master-clock mode CLKM/S=+5V. The CLKIO becomes a clock output for synchronizing with other devices. This is also correctly reflected in the schematic.

For a 2xBTL configuration, the output configuration pins should be hardwired (or connected through a resistor, such as R1 in the schematic) to MSEL0=+5V and MSEL1=GND. Left floating (e.g. MSEL1 is not grounded by J1 and R2 not mounted) the device is left in an invalid state.

What is mandatory though, is PVDD decoupling close to the device. In the schematic, this is missing. Low ESR ceramic capacitors of 1UF to 10UF should be placed close to the PVDD pins, and connected directly to GND.

Generally, all supply pins should be decoupled as close to the device as possible.

Also a larger bulk (electrolytic) capacitance should be placed relatively close to the device, ensuring good PVDD supply “stiffness” if power is delivered over relatively long lines.

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2 Replies
Audio-guru-CPH
Employee
5 solutions authored 25 sign-ins 10 replies posted
Employee

Using 10kohm resistors for pull-up on I/O pins should work perfectly fine, but can be omitted by directly hardwiring to +5V. No series resistor is need. The input impedance of the I/O pins are very high.

The MA12070 should power up without any programming/controller. ENABLE pin should be tied low and MUTE brought up slowly by an RC network, ensuring no click/pops when starting up.

This is done correctly by R3/C24 in the schematic.

The device should be in master-clock mode CLKM/S=+5V. The CLKIO becomes a clock output for synchronizing with other devices. This is also correctly reflected in the schematic.

For a 2xBTL configuration, the output configuration pins should be hardwired (or connected through a resistor, such as R1 in the schematic) to MSEL0=+5V and MSEL1=GND. Left floating (e.g. MSEL1 is not grounded by J1 and R2 not mounted) the device is left in an invalid state.

What is mandatory though, is PVDD decoupling close to the device. In the schematic, this is missing. Low ESR ceramic capacitors of 1UF to 10UF should be placed close to the PVDD pins, and connected directly to GND.

Generally, all supply pins should be decoupled as close to the device as possible.

Also a larger bulk (electrolytic) capacitance should be placed relatively close to the device, ensuring good PVDD supply “stiffness” if power is delivered over relatively long lines.