Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

Class D Audio Amplifier IC Forum Discussions

Ravi
Level 1
Level 1
10 sign-ins First reply posted First like given

Hello,

I would like to design a PCB for the MA12070 IC. I have following queries. Kindly help me with them. Thanks in advance!

1. Datasheet recommends a micro-controller based power-up and power-down logic. However, is it ok to tie the nENABLE pin directly to GND and connect the nMUTE circuit to a P5V-680E-1M-47uF-GND circuit with anode of a diode connected to the join of R-C and cathode connected to the join of R-R for fast turn-off? Something similar to that recommended by the TDA7293/4 IC datasheet.

2. To avoid device failure due to inrush current, the Errata sheet recommends 'schottky diode to be connected at the output of each node.' Is is correct to assume that a the cathode of schottky diode be connected directly to the output pin and the anode to ground?

3. To avoid device failure due to PVDD hot plugging, the Errata sheet suggests a power supply with soft start function. Is it correct to assume that the solution to this can be the circuit in Fig. 5 of the Demo_BassAmp note using two IRF9358 MOSFETS?

4. Is it correct to assume that points 2 and 3 are mutually exclusive and that suggestions in both 2 and 3 above should be implemented?

5. Does the device operate and perform better with an external heat-sink in addition to the copper connected to the IC thermal pad?

Thanks again!

0 Likes
1 Solution
amusz
Employee
Employee
5 solutions authored 10 replies posted 10 sign-ins

Hello @Ravi ,

1 - It is okey to proceed with the mentioned configuration always that the recommended and abs max rating for these pins are considered. The most important is that the levels at these pins are high (3.3V) or low (GND or 0V).

2 - Please see a picture of this configuration below:

amusz_0-1673633108406.png

3 - The simplest solution is to add some series resistance trough the PVDD track 100mohm with 400uF should be enough to provide to RC time. Example below:

amusz_1-1673633210430.png

4 - Correct, both should be implemented.

5 - It's not that it's necessarily works better, but a heatsink will just allow more continuous output power if needed. Please see this application note about this topic here

 

 

 

View solution in original post

3 Replies
amusz
Employee
Employee
5 solutions authored 10 replies posted 10 sign-ins

Hello @Ravi ,

1 - It is okey to proceed with the mentioned configuration always that the recommended and abs max rating for these pins are considered. The most important is that the levels at these pins are high (3.3V) or low (GND or 0V).

2 - Please see a picture of this configuration below:

amusz_0-1673633108406.png

3 - The simplest solution is to add some series resistance trough the PVDD track 100mohm with 400uF should be enough to provide to RC time. Example below:

amusz_1-1673633210430.png

4 - Correct, both should be implemented.

5 - It's not that it's necessarily works better, but a heatsink will just allow more continuous output power if needed. Please see this application note about this topic here

 

 

 

Ravi
Level 1
Level 1
10 sign-ins First reply posted First like given

Hello amusz,

Thank you for the early reply.

Solutions to all my queries are now clear to me.

I'll proceed to make an application board and share my findings later.

Thanks again!!

 

0 Likes
Ravi
Level 1
Level 1
10 sign-ins First reply posted First like given

Hello again,

Your reply raises one more question:

You mentioned that the logic high level should be 3.3V.  However, as per the datasheet, the absolute maximum value for MSEL0, MSEL1, nMUTE, nENABLE, nClip,  nERROR, SCL, SDA, CLKM/S, CLKIO, AD0 and AD1 is 6V.

In order to avoid another supply in the form of a 3.3V supply, is it OK to use 5V for the above mentioned IOs?

Thanks!

0 Likes