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Class D Audio Amplifier IC Forum Discussions

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I've been assigned with debugging an existing 4-channel class-d amplifier based on IRS2093. Details and questions below. My idea was to put all questions in one post but if this is not desired then just let me know.  

Details for the current design: 
Class-D Driver: IRS2093MPbF
MOSFET: IRFB5615 (one pair per channel)
Topology: half-bridge
Fsw: 380 KHz
Dead-time: 105 ns. 
Vcc: 15V
Gate stoppers: 10 Ohm
Rail voltage: just under 100V (2 x 48,5V)

Junction temperature
One of the first things I noticed is that the IRS2093 runs quite hot, too hot for my taste. 
I did not do extensive testing but a quick test with opened case @ room temperature (much better cooling than worst case) gave me around 90 degrees celcius on the FLIR on the IRS2093. If I take into account the the unit will be running with the lid closed and the heatsink reaching > 70 degrees in worst case conditions then my best guess is that the IC is running too hot. 

I wanted to get a better picture of the power dissipation in our design, so I decided to check the math as described in Application Note AN-1146 - Junction Temperature Estimation. I got stuck on: 

7.4 PLSH: Power Dissipation of the High-side Level Shifter

PLSH = 0.4nC x fsw x VBUS x 4

All is clear except "nC". What is nC supposed to be?
I suspected the Mosfet Gate charge but that doesn't make sense as in the rest of the calculations, the gate charge is refered to as Qg. 

Anyway, in order to cool down the IC, my idea was to: 

- reduce Vcc from 15V to 12V. Sounds good?
- if that is not enough, reduce Fsw and/or rail voltage, find compromise between performance and reliability.  

The IRFB5615 have a gate charge of 27nc, seems like this should not pose a major issue for this IC?  

Feedback resistor. 
The Application Note AN-1146 shows a nice table for setting Fsw, assuming a feedback resistor of 47k. 

The design I'm working on seems to be loosely based on IRAUDAMP8 which uses Rfb = 100k. 
Not sure why the AN says to use 47k and IRAUDAMP8 uses 100k? There's not a lot of info to work with here so I guessed I'd better ask. 

DT is set to the highest value (105ns) which seems like quite a lot to me for IRFB5615 but I have yet to check double check if it can be reduced. My guess is that if it can be reduced, THD will drop but it won't solve the issue of the IRS2093 running so hot? 
I checked the THD and that seams to be OK (all things considering), the lowest being around 0,02% @ 50W. 

Output power
The amplifier was designed to do 4 x 200W @ 4 ohm or 4 x 300W @ 2 Ohm <= 1% THD, 1 KHz and in fact it does (at least for a short period).  My guess is that if we run 2 channels on 4 Ohm and two channels on 2 ohm, the 2 Ohm power rating will go up considerably, well exceeding 300W per channel which seems a bit much to me? Maybe pushing the limits of these devices? 

Over Current Protection
OCP is disabled in the current design and I would rather enable it if possible. However the Application note says: 

2. Switching Speed
Internal over current protection has a certain time window to measure the output current. If switching
transition takes too long, the internal OCP circuitry starts monitoring voltage across the MOSFET which
induces false triggering of OCP. Less than 20nC of gate charge per output is recommended.

The IRFB5615 have a gate charge of 27nc so we can't (or shouldn't) enable OCP? 
The word "recommended" leaves room for interpretation.  

Final note: Please note that this is not my design and that I'm quite new to class-d amplifier design. Just trying to learn and improve the existing design. So if you have any additional suggestions I'd be more than welcome to hear them. 


5 Replies

For dead time; 105nS is so long and it will made most odd harmonic wave for output. My favorite is 0 to 15nS.

For gate drive power, 12V is better for the mosfet.

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Thank you for your kind reply! 
Yes we know dead time is probably too high, we will check later if it can be reduced.
I just noticed that for the IRS2093 there is a discrepancy between the datasheet and the application note: 

Application note AN-1146, P21 
Class-D controller: IRS2093M
Deadtime range according to Fig. 17: 105/75/45/25 ns. 

Class-D controller: IRS2093M
Deadtime range according to Fig. 17: 105/85/65/45 ns. 

Datasheet, P1 & P9
Class-D controller: IRS2093MPbF
Deadtime range according to datasheet: 105/85/65/45 ns. 

I'm guessing the Datasheet is correct and the Application Note is not?
In any case the minimum is either 25 or 45 and we can't get any lower, correct? 
Or am I misunderstanding something? 

Gate driver: yes we will reduce to 12V, thank you for confirmation. Any feedback on the calculation of: 

PLSH = 0.4nC x fsw x VBUS x 4

I'd really like to know what nC stands for.


Thanks for your comments.

2093 have four step for setup. As different application and thinking, engineer have different favorty. So you can see different.

The rule of the total(system) dead time, include drive IC dead time and switching delay time.

Change MOSFET/ dead time and Rg on & off, you can got different tone colour.

Need better change for meet your costomer and application.

50 replies posted 25 solutions authored 10 likes received

Hello @w_wever,

The minimum dead time on IRS2093 is 45ns. This is the narrowest you can use the device.
Dead time should be set to complete ZVS operation at idling to make it most efficient. Monitor VS node waveform and make sure ZVS is not disrupted by insufficient deadtime length.

0.4nC is the charge amount level shifter needed to do the job internally




Dear Nishanth:

Class-D is radio application. It is very different. Sound and listener feel is very inportant. As long delay time, it will output most 3/5/7... harmonic. It will go hard if it is high than 0.01%.

So we had set: