About "CSD"

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
lixia
Level 2
Level 2
25 sign-ins 10 replies posted First like received

Hi

@Liz

I have an idea, do not know whether it is feasible, my purpose is as follows:

1, the capacitor CT is set to 47uf-68uf, the purpose is when overcurrent occurs, after a delay of a period of time, let the MOSFET fully dissipate heat, IRS2092 automatically restarts, this process repeats.

2, Ct increases, resulting in an excessively long IRS2092 startup time, so I plan to increase Q1, R1, by controlling Q1 open about 50-80ms time (50-80ms after Q1 off), charge Ct, accelerate Vcsd voltage rise time, that is, accelerate IRS2092 start time. Will this design damage irs2092? What's the downside?

3, SD can control IRS2092 shutdown. 

The above is an idea of mine, I don't know if it is feasible?

 

0 Likes
1 Solution
Sodum
Moderator
Moderator
Moderator
50 solutions authored 250 sign-ins 10 likes given

Hello @lixia ,

The circuit you proposed won't damage the IC, until the voltage on CSD pin is in the range of VAA-VSS.

But this circuit will create "Click Noise Issue" as you are reducing Tsu(Tsu is the amount of time between powering up the IC in shutdown mode to the moment the IC releases shutdown to begin normal operation). So this circuit configuration is not recommended by us.

Regards, 

Premsagar S

View solution in original post

0 Likes
6 Replies
Sodum
Moderator
Moderator
Moderator
50 solutions authored 250 sign-ins 10 likes given

Hello @lixia ,

Thank you for contributing to Infineon Community.

The circuit you proposed is good, but has the following limitations,

  • This IC has a click noise elimination feature during Turn on & turn off. The Ct capacitor should be selected such that CSD pin has a slow enough ramp up from Vth2 to Vth1, such that the voltages in the capacitors can settle to their target values. Decreasing the Tsu (by turning ON Q1 as shown in the figure above) may cause issues with the click noise elimination feature. 
  • In addition when there is an overcurrent fault, the time Treset & Tsu will help to dissipate the heat. To avoid overheating the MOSFETs from the repetitive sequence of shutting down and resuming operation during overcurrent conditions, these timing should be kept as recommended. The minimum Treset is recommended to be 0.1Sec. 

Regards,

Premsagar S

0 Likes
lixia
Level 2
Level 2
25 sign-ins 10 replies posted First like received

Thank you so much!

1、Ct is set to 47uf-68uf to meet your second "In addition when there is an overcurrent fault, the time Treset & Tsu will help to dissipate the heat. ", which caused the problem of slow startup time. So plan to design Q1 and R1.

2、 What I want to know is whether the Q1 and R1 circuits will break the IRS2092.

3、For what you said, "This IC has a click noise elimination feature during Turn on & turn off" My plan is that Q1 is only open for 50ms-80ms, and then Q1 is turned off. My concern is whether the process of charging Ct over Q1 and R1 will break the IRS2092?.

0 Likes
Sodum
Moderator
Moderator
Moderator
50 solutions authored 250 sign-ins 10 likes given

Hello @lixia ,

The circuit you proposed won't damage the IC, until the voltage on CSD pin is in the range of VAA-VSS.

But this circuit will create "Click Noise Issue" as you are reducing Tsu(Tsu is the amount of time between powering up the IC in shutdown mode to the moment the IC releases shutdown to begin normal operation). So this circuit configuration is not recommended by us.

Regards, 

Premsagar S

0 Likes
lixia
Level 2
Level 2
25 sign-ins 10 replies posted First like received

hi @Sodum 

Thank you very much。

1, tsu is too short may produce a "Click Noise Issue" at the time of IRS2092 power-up. I will try to adjust the time of Q1 opening and try to adjust this time as much as possible, as long as it does not damage it.

2, AN-1138 mentioned tsu is determined by Ct, but AN-1138 mentions "Figure 11 Latched Protection with Reset Input" and "Figure 12 Interfacing with Host Controller" two methods "Latched Protection", there is no Ct, how to prevent "Click Noise" Issue”。

22.png222.png

0 Likes
Sodum
Moderator
Moderator
Moderator
50 solutions authored 250 sign-ins 10 likes given

Hello @lixia ,

The details of Click Noise elimination feature are mentioned on page no 4 & 5 of application note AN-1138. Tsu is one of the contributing factors for click noise elimination. 

Sodum_0-1664168590994.png

The capacitor Ct recommendation is given based on the charging & discharging rate of the internal circuit and considering all the features & functions of the IC. In the application note none of the typical circuit recommends to charge  Ct externally. 

If you want to charge Ct externally to reduce Tsu, please test for click noise and temperature rise. However this configuration is not recommended by Infineon.

Regards,

Premsagar S 

 

0 Likes
lixia
Level 2
Level 2
25 sign-ins 10 replies posted First like received

Got it, thank you very much.

 

lixia_1-1664171904101.png