Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

CAPSENSE™ & MagSense

mjbinstead
Level 1
5 sign-ins First like received First reply posted
Level 1

I am trying to locate Cypress documentation for low-level PSoC 62 CapSense registers and how to use them.
I have found  mid-level and high-level documentation.

I have created a working design based on the CY8CPROTO_062_4343W and the CapSense library.

My design does not fit in with the available CapSense sensor types but it does use the CapSense sensing hardware.

Currently I am using the CapSense library to collect the touch data for one of the standard CapSense sensor types, but I am having to modify the behaviour within the pre and post interrupt calls to fit in with the new design.

I do appreciate how much work has gone into the CapSense library and how it is protecting me from the low-level details and chip variations.

 

0 Likes
1 Solution
Hari
Moderator
Moderator 750 replies posted 500 replies posted 250 solutions authored
Moderator

Hello @mjbinstead 

 

These registers are not provided to the public as they are proprietary and reveal the IP's internal working. Please let me know if there is anything specific that you are trying to achieve using these registers. Note that we have low-level APIs that read out most of the information measured by the hardware and you can check them out in the middleware API documentation. 


Best regards,

Hari

View solution in original post

0 Likes
7 Replies
MotooTanaka
Level 9
First comment on KBA 1000 replies posted 750 replies posted
Level 9

Hi,

 

I think that you need both Technical Reference Manual (TRM)

and Register Technical Reference Manual (Register TRM) .

 

There are 3 kinds of PSoC 62

Flash 512KB CY8C62x5

Flash 512KB - 1024KB CY8C63x6, CY8C63x7

Flash 1024KB - 2048KB CY8C62x8, CY8C62xA

So get the Register TRM for your device.

 

PSoC 62 Architecture Technical Reference Manual
https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-te...

 

PSoC 62 MCU with Bluetooth LE: CY8C63x6, CY8C63x7 Registers Technical Reference Manual
https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-cy8c63x6-cy8c63x7-cy8c6...

 

PSoC 6 MCU: CY8C62x8, CY8C62xA Registers Technical Reference Manual
https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-cy8c62x8-cy8c62xa-regis...

 

PSoC 6 MCU PSoC 62 Register Technical Reference Manual (CY8C62x5)
https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-techni...

 

moto

0 Likes
mjbinstead
Level 1
5 sign-ins First like received First reply posted
Level 1

Thanks - I am familiar with most of these documents

however they don't seem to include a description of the CSD registers.

The CapSense library accesses the CSD sub-system via a structure shown below,

but I have been unable to find a low-level description of this group of registers.

 

/**
* \brief Capsense Controller (CSD)
*/
typedef struct {
__IOM uint32_t CONFIG; /*!< 0x00000000 Configuration and Control */
__IOM uint32_t SPARE; /*!< 0x00000004 Spare MMIO */
__IM uint32_t RESERVED[30];
__IM uint32_t STATUS; /*!< 0x00000080 Status Register */
__IM uint32_t STAT_SEQ; /*!< 0x00000084 Current Sequencer status */
__IM uint32_t STAT_CNTS; /*!< 0x00000088 Current status counts */
__IM uint32_t STAT_HCNT; /*!< 0x0000008C Current count of the HSCMP counter */
__IM uint32_t RESERVED1[16];
__IM uint32_t RESULT_VAL1; /*!< 0x000000D0 Result CSD/CSX accumulation counter value 1 */
__IM uint32_t RESULT_VAL2; /*!< 0x000000D4 Result CSX accumulation counter value 2 */
__IM uint32_t RESERVED2[2];
__IM uint32_t ADC_RES; /*!< 0x000000E0 ADC measurement */
__IM uint32_t RESERVED3[3];
__IOM uint32_t INTR; /*!< 0x000000F0 CSD Interrupt Request Register */
__IOM uint32_t INTR_SET; /*!< 0x000000F4 CSD Interrupt set register */
__IOM uint32_t INTR_MASK; /*!< 0x000000F8 CSD Interrupt mask register */
__IM uint32_t INTR_MASKED; /*!< 0x000000FC CSD Interrupt masked register */
__IM uint32_t RESERVED4[32];
__IOM uint32_t HSCMP; /*!< 0x00000180 High Speed Comparator configuration */
__IOM uint32_t AMBUF; /*!< 0x00000184 Reference Generator configuration */
__IOM uint32_t REFGEN; /*!< 0x00000188 Reference Generator configuration */
__IOM uint32_t CSDCMP; /*!< 0x0000018C CSD Comparator configuration */
__IM uint32_t RESERVED5[24];
__IOM uint32_t SW_RES; /*!< 0x000001F0 Switch Resistance configuration */
__IM uint32_t RESERVED6[3];
__IOM uint32_t SENSE_PERIOD; /*!< 0x00000200 Sense clock period */
__IOM uint32_t SENSE_DUTY; /*!< 0x00000204 Sense clock duty cycle */
__IM uint32_t RESERVED7[30];
__IOM uint32_t SW_HS_P_SEL; /*!< 0x00000280 HSCMP Pos input switch Waveform selection */
__IOM uint32_t SW_HS_N_SEL; /*!< 0x00000284 HSCMP Neg input switch Waveform selection */
__IOM uint32_t SW_SHIELD_SEL; /*!< 0x00000288 Shielding switches Waveform selection */
__IM uint32_t RESERVED8;
__IOM uint32_t SW_AMUXBUF_SEL; /*!< 0x00000290 Amuxbuffer switches Waveform selection */
__IOM uint32_t SW_BYP_SEL; /*!< 0x00000294 AMUXBUS bypass switches Waveform selection */
__IM uint32_t RESERVED9[2];
__IOM uint32_t SW_CMP_P_SEL; /*!< 0x000002A0 CSDCMP Pos Switch Waveform selection */
__IOM uint32_t SW_CMP_N_SEL; /*!< 0x000002A4 CSDCMP Neg Switch Waveform selection */
__IOM uint32_t SW_REFGEN_SEL; /*!< 0x000002A8 Reference Generator Switch Waveform selection */
__IM uint32_t RESERVED10;
__IOM uint32_t SW_FW_MOD_SEL; /*!< 0x000002B0 Full Wave Cmod Switch Waveform selection */
__IOM uint32_t SW_FW_TANK_SEL; /*!< 0x000002B4 Full Wave Csh_tank Switch Waveform selection */
__IM uint32_t RESERVED11[2];
__IOM uint32_t SW_DSI_SEL; /*!< 0x000002C0 DSI output switch control Waveform selection */
__IM uint32_t RESERVED12[3];
__IOM uint32_t IO_SEL; /*!< 0x000002D0 IO output control Waveform selection */
__IM uint32_t RESERVED13[11];
__IOM uint32_t SEQ_TIME; /*!< 0x00000300 Sequencer Timing */
__IM uint32_t RESERVED14[3];
__IOM uint32_t SEQ_INIT_CNT; /*!< 0x00000310 Sequencer Initial conversion and sample counts */
__IOM uint32_t SEQ_NORM_CNT; /*!< 0x00000314 Sequencer Normal conversion and sample counts */
__IM uint32_t RESERVED15[2];
__IOM uint32_t ADC_CTL; /*!< 0x00000320 ADC Control */
__IM uint32_t RESERVED16[7];
__IOM uint32_t SEQ_START; /*!< 0x00000340 Sequencer start */
__IM uint32_t RESERVED17[47];
__IOM uint32_t IDACA; /*!< 0x00000400 IDACA Configuration */
__IM uint32_t RESERVED18[63];
__IOM uint32_t IDACB; /*!< 0x00000500 IDACB Configuration */
} CSD_V1_Type; /*!< Size = 1284 (0x504) */

// For the  CY8C624ABZI_S2D44 these registers are located at 0x40360000.

#define CSD0_BASE 0x40360000UL
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */

 

 

 

 

 

0 Likes
MotooTanaka
Level 9
First comment on KBA 1000 replies posted 750 replies posted
Level 9

Hi,

 

Thanks - I am familiar with most of these documents

> however they don't seem to include a description of the CSD registers.

I'm sorry, I have been thinking that they should be in the Registers TRM,

but, yes,  you are correct, I could not find registers whose address is starting from 0x4036xxxx.

 

I'm afraid that information you need have be be obtained from Cypress.

I hope that someone in Cypress will reply to this discussion.

 

moto

0 Likes
mjbinstead
Level 1
5 sign-ins First like received First reply posted
Level 1

thanks moto - I had reached out to cypress and created a "mycase" - they suggested I create a developer thread - if I hear from 'mycase" I will add a link here for others to use.

Hari
Moderator
Moderator 750 replies posted 500 replies posted 250 solutions authored
Moderator

Hello @mjbinstead 

 

These registers are not provided to the public as they are proprietary and reveal the IP's internal working. Please let me know if there is anything specific that you are trying to achieve using these registers. Note that we have low-level APIs that read out most of the information measured by the hardware and you can check them out in the middleware API documentation. 


Best regards,

Hari

0 Likes
mjbinstead
Level 1
5 sign-ins First like received First reply posted
Level 1

Hi Hari, I will send you patent details of what I am working on via my existing "mycase".

0 Likes
mjbinstead
Level 1
5 sign-ins First like received First reply posted
Level 1

Hi Hari, Can you un-cancel "mycase" so I can send you details ?

0 Likes