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CAPSENSE™ & MagSense



this is a follow-up to a previous post on placing a PSoC right under a CSX touchpad in applications with limited space.

I have a first iteration of such a design, but there are a few things I worry may affect the signal quality of the touchpad. It is made out of 2 PCBs linked together with castellated holes. The first PCB is the PSoC module with castellated holes, and the second one is the touchpad, with mounting pads to solder the module on top.

Here is a view of the stackup to better understand the intended device


The capsense pcb has 4 layers: 2 first are for the touchpad, the 3rd has a ground hatch to protect signal integrity, and bottom layer has  the pads for the castellated holes.

1. The PSoC PCB could be 2 layers, but I made it 4 just so I could add a second hatch ground to isolate capsense signals even more. Is this a good thing, or I just risk stealing to many field lines from capsense to ground?

In the image below, we can see my TX lines and their filtering resistors close to the RX lines, and close to the star ground


2. Now, should I move the TX lines closest to the star ground, increasing the distance from RX lines, or move them closer to the RX lines and separate them with a trace connected to VSS capsense?

3. Another point I want to address is how sensitive and critical are the CIntX capacitors. in the image below, we see that I have I2C lines moving right next to the  CIntA and CIntB capacitors.


can this be an issue? should I keep fast signals away from the capacitors? the space limitation pretty much forces me to do so. I also placed a via for each of the 2 CIntX capacitors, and this eats away a little bit of space. Could I join the 2 capacitors to the save via like so?



4. I did not put a single ground or power plane on the PCB, to prevent field line sinking on the touchpad. Could this be an issue given that the ground comes from supply and follows a single trace all the way to the star ground?



Thanks a lot!

1 Solution

Hi @jcsb1994,

1. One hatched GND layer is enough to isolate the CapSense layers from other layers.

2. Maximum distance possible between TX and RX lines is recommended. It is advisable to move TX and RX further apart. The distance between them should at least be 10mil (higher the better). However, a VSS trace must be present in between TX and RX traces if that is not possible. Make sure that the 560ohm series resistors on the CapSense pins are as close to the MCU pins as possible.

3. I2C lines (or any other switching signal traces) must not be close to the CapSense traces and CapSense capacitors as they induce noise into the CapSense system.
>>> I2C traces must be kept away from the capacitors. The I2C lines may be routed in a different layer and the hatched GND plane would reduce their effect on CapSense traces.
>>> Yes, the VSSA pins may be "joined" as indicated.

4. It would not be an issue. However, follow the guidelines of section 7.4.10 in CapSense Design Guide


Best regards,

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