Dear all,
I already own a CYW20706B2 Evaluation KIT. I want to connect it to an Audio codec and use the share-clock feature on CYW20706(GPIO BT_CLK_REQ/P4/P24) as MCLK (Master clock) for driving the Audio codec.
As i know, the default state of this GPIO is BT_CLK_REQ enabled, with double checking i can make sure that no more configurations for this GPIO in my project. However, when i connect the Logic Analyzer to pin 3 (J19) or pin 5 (J21) to visualize the output clock then nothing happen, there is no clock pulse.
I would really appreciate if anyone could give me a hand on how to reconfigure this Share-clock feature.
