Share-Clock Application

[anhnhancao]

Dear all,

I already own a CYW20706B2 Evaluation KIT. I want to connect it to an Audio codec and use the share-clock feature on CYW20706(GPIO BT_CLK_REQ/P4/P24) as MCLK (Master clock) for driving the Audio codec.

As i know, the default state of this GPIO is BT_CLK_REQ enabled, with double checking i can make sure that no more configurations for this GPIO in my project. However, when i connect the Logic Analyzer to pin 3 (J19) or pin 5 (J21) to visualize the output clock then nothing happen, there is no clock pulse. 

I would really appreciate if anyone could give me a hand on how to reconfigure this Share-clock feature.

[DheerajPK_41]

Let me check and get back to you.

[anhnhancao]

Thank you very much for your help, looking forward to receiving an answer to this topic.

[AB]

I am also waiting for receiving an answer on this.

[AB]

Based on the datasheet of another chip (BCM43303) it appears like it could be used for sleep mode indication. I am not sure if for this chip also BT_CLK_REQ does the same. Here is the quote from the datasheet.

"Reference clock request output signal for WLAN/BT. Leave this pin as a no connect when using a dedicated crystal. For clock sharing with a TCXO, the signal is active-high by default when the BCM43303 is requesting the reference clock. The signal goes low when the reference clock is not needed (that is, in sleep mode). Provide an external 100 kΩ pull-down to this pin to prevent it from floating during reset."

[DheerajPK_41]

Update:

BT_CLK_REQ configuration cannot be done on 20706, since it is not supported in the lower stack. We will try to support it in the upcoming SDKs. 

FYI. We can use ACLK for providing MCLK. ACLK is available on P32, P33, P36, and P37.