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When less can be more – with Smart Module Design (Part 1)

Jan_B
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When less can be more – with Smart Module Design (Part 1)

How thermal performance challenges from chip shrinkage are overcome by IGBT module layout improvements 

Size and power often seem like opposite sides of a coin. When you reduce size – one of the ever-pressing goals in our industry – you inevitably reduce power. But does that have to be the case? By shifting our thinking from the chip to the module design, there’s no need to flip a coin.

In IGBT modules, chip shrinkage leads to an increased thermal impedance, which then impacts performance. But since smaller chips free up more space on the substrate, it is possible to use this newly available space to optimize the layout of the module. In this article, we’ll look at how adapting the module design can improve thermal performance. Part 2 of this article will look at improving electrical performance.

For reference, we’ll be using the new 1200 V, 600 A EconoDUAL™ 3 module with TRENCHSTOP™ IGBT 7 technology, which is optimized for applications like general-purpose drives (GPD), commercial, construction and agricultural vehicles (CAV), uninterruptible power supplies (UPS), and solar.

Thermal challenges with smaller chips

The 1200 V TRENCHSTOP™ IGBT 7 medium-power technology features a chip shrinkage of about 30% compared to the former IGBT 4 technology. Smaller is generally better, but a smaller chip in an unchanged reference module means that more current is drawn from the same chip area. This leads to an increased thermal impedance from the chip junction to the heat sink. To compensate, you could use highly conductive substrate materials, improve the baseplate contact to the heat sink, or use highly conductive thermal interface material. However, such materials lead to higher costs, so they are often not the first choice for designers.

But everyone likes something free, right? So let’s turn our attention to the “free” space on the substrate. Thirty percent smaller chips result in more available space on the substrate. Now how can we use this newly freed-up space from chip shrinkage to improve thermal impedance?

First of all, thermal impedance from junction to heat sink is defined by the conductivity and thickness of each contributing layer and – more importantly for this example – by the effect of heat spreading within the layers. Whether the heat spreading or the higher resistance of thicker conductive layers dominates, depends on the layer thickness, its conductivity, and the amount of heat spreading.

In medium-power modules like the EconoDUAL™ 3, multiple chips are connected in parallel to achieve high module currents. Due to this parallelization, more than one chip is coupled in the thermal stack. The heat fronts from both chips overlap at a certain point in the module, which leads to a reduced effective coupling area for both of the chips (Figure 1).

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Optimizing IGBT module layout for improved thermal performance

Modules with massive copper baseplates are less dependent on the distance between the chips since the copper provides a thick, highly conductive thermal path to the heat sink. However, in combination with other steps to optimize the module layout, chip placement can make a significant impact.

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In Figure 2, you can see the difference chip placement makes on two EconoDUAL™ 3 module layouts with the same thermal stack. In addition to optimizing the placement of the chips, the layout of the direct bonded copper substrates (DBCs) can also have an impact. By the usage of three smaller DBCs in module layout V2 - instead of the two larger DBCs in V1, the baseplate can be optimized for lower cavities, thus improving the thermal contact to the heat sink.

To see how chip shrinkage, module layout, and DBC combine to impact the overall thermal impedance (Rth,jh), we measured their effect on various IGBT 4 and IGBT 7 module layouts. In the second column of Figure 3 (IGBT7, Module layout V1, DBC #1), you can see that by simply shrinking the chip size without any change to the layout, the IGBT Rth,jh increases by about 20%.

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We go one step further in the third column (IGBT7, Module layout V2, DBC #1) to show the impact of changing the module’s internal layout from 2 to 3 DBCs like shown in Figure 2. This demonstrates that by means of module layout, the impact of a 30% chip shrinkage can be limited to an IGBT junction-to-heat sink Rth,jh increase of 10% (IGBT7, Module layout V2, DBC #1).

To also address applications that require higher isolation voltage, an increase of the DBC ceramic thickness can be realized. The last column of Figure 3 (IGBT7, Module layout V2, DBC #2) represents the new design with thicker ceramic: the already-available 1200 V TRENCHSTOP™ IGBT 7.

In Part 2 of this article, we’ll move from thermal performance to improving electrical performance in relation to chip shrinkage.

Stay tuned! 🙂