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Unleashing the potential of combining Smart I/O and SPI

Unleashing the potential of combining Smart I/O and SPI

RodolfoGL
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Greetings, tech enthusiasts!

Today, I invite you on a journey into the captivating world of embedded systems, where we'll explore a fascinating yet underrated aspect of the latest PSoCTM family of devices. Picture this: a block called Smart I/O, quietly hidden away amidst the excitement surrounding the beloved Universal Digital Blocks (UDBs). But let me tell you, my friends, the Smart I/O block holds immense potential and deserves our attention.

In this blog post, we'll uncover the hidden capabilities of Smart I/O and its remarkable synergy with the Serial Communication Block (SCB). Together, they empower us to create new digital interfaces that may not be native to the PSoCTM platform. Yes, you heard it right! By combining Smart I/O with the Serial Peripheral Interface (SPI), we can unlock a realm of possibilities and enable unconventional digital interfaces that were previously beyond reach.

So first, let’s review what is inside of the Smart I/O block and how it is connected to the SPI interface.

Smart I/O elements + SPI block

SmartIOelementsSPIblocks.PNG

The Smart I/O has two major components:

  • 1x Data unit (DU): consists of a simple 8-bit datapath. It is capable of performing simple increment, decrement, shift and AND/OR operations.
  • 8x Lookup table (LUT): consists of a three-input LUT and a flip-flop. The inputs can be the DU output, any of the SPI signals (SCK/MOSI/MISO/SS), any of the GPIOs (A/B/C/D), or any of LUTs output. The logic enforced by the LUT can be sequential (requires a clock) or combinational (no clock).

Note that the direction of the SPI signals depend on how the SPI block is configured – Master or Slave. Basically, the idea is to manipulate the SPI lines to implement a new custom interface. The SPI block works as serializer to push/pull data to/from the CPU.  And the Smart I/O can delay or change the behavior of any of the SPI signals to conform with the new desired digital interface.

In the next sections, you can find some examples.

Inter-IC Sound (I2S)

The I2S is a serial bus interface standard used to connect digital audio devices together. It is very similar to the SPI in terms of clock and data, however it requires a continuous flow of data and the word select signal to indicate if the data is left or right.

The I2S frame has the following format:

Signal

Word 0

Word 1

Word 2

Word 3

Word 4

SD

(data)

16 or 32-bit value

16 or 32-bit value

16 or 32-bit value

16 or 32-bit value

16 or 32-bit value

WS

1 : Left

0 : Right

1 : Left

0 : Right

1 : Left

 

The following signal mapping is established between SPI and I2S signals.

SPI signals

I2S signals

SCLK

SCK

MOSI

SDO

MISO

SDI

SS

WS

 

  • I2S Master

 Summary:

The SPI clock and data can be directly mapped to the I2S clock and I2S data. However, the SPI slave select has to be translated to the I2S word select. For that, the Data Unit is configured to toggle every 64 or 32 cycles, depending if the I2S word width is 32-bits or 16-bits, respectively.

The I2S sample rate can be calculated as:

 
RodolfoGL_9-1685104985709.png

 

Note that in the example above, the SPI MOSI signal is mapped to the I2S SD signal, which can be an input or output, depending if the I2S FIFO is configured as RX or TX. In case the I2S SD is configured as an input, it should be mapped to the SPI MISO signal.

 

SPI Config:

Mode: Master

Sub mode: Motorola

SCLK mode: CPHA = 0, CPOL = 1

Data rate (kbps): 3072 / 2048 / 1024 / 768 / 512 / 256

Oversample: 4

Bit order: MSB first

Rx/Tx data width: 16 bits

SS polarity: Active low

Clock: 4x the data rate

SPI time diagram

 

SmartIOandSPI.II.PNG

 

I2S time diagram

SmartIOandSPII.PNG

Smart I/O Config:

Data unit:

Input: LUT1 (reset) / LUT2 (enable)

Opcode: Increment and wrap

DATA0: Constant 0

DATA1: DATA Register

Register value: 63 or 31

Size: 6-bits or 5-bits size/width operand

LUT0:

Input: Chip 0 (SPI.mosi)

Mode: Sequential (gated) output

Logic: Input = Output

Output: I/O 0 (I2S.sd)

 

LUT1:

Input: Chip 3 (SPI.ss)

Mode: Combinational output

Logic: Input = Output

Output: Logic to reset DU

 

LUT2:

Input: Chip 2 (SPI.sclk)

Mode: Sequential (gated) output

Logic: Input = Output

Output: I/O 2 (I2S.sck)

 

LUT3:

Input: DU / LUT3

Mode: Sequential (gated) output

Logic: Toggle when DU asserts

Output: I/O 3 (I2S.ss)

 

Clock:

Same clock as the SPI

 Example:

You can find an example of an I2S Master implementation using SPI + Smart I/O here (configured as TX):

https://github.com/Infineon/mtb-example-psoc6-smartio-i2s

 

  • I2S Slave

 Summary:

The I2S slave implementation with SPI + Smart I/O is relatively similar to the I2S master. The two major differences are:

1)        The SPI shall be configured as slave

2)        The logic to map the SPI.SS to I2S.WS is different. When the WS signal toggles for the first time, the SS should be asserted and stay asserted.

Example:

There is no example available to demonstrate this interface. If you are interested to find a solution for the I2S Slave, please contact Infineon or leave a message in this blog post.

 

Serial General Purpose Input/Output (SGPIO)

The SGPIO interface is a four-signal bus defined in the SFF-8485 standard. It is typically used in the backplane controllers to control LEDs and check the disk drive status. Each drive requires 3-bits in a SGPIO frame. The SGPIO master is known as SGPIO initiator and the SGPIO slave is known as SGPIO target. The interface has the following signals:

  • SClock: clock signal driven by the SGPIO initiator
  • SLoad: indicates the beginning of a frame. It can also contain some vendor 4-bit value (L0~3). It is driven by the SGPIO intiator
  • SDataOut: serial data output bit stream driven by the SGPIO intiator
  • SDataIn: serial data input bit stream driven by the SGPIO target

The SGPIO frame has the following format:

Signal

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Bit8

Bit9

SLoad

1

L0

L1

L2

L3

0

0

0

0

0

SDataOut

ODN 2

OD0

0

OD0

1

OD0

2

OD1

0

OD1

1

OD1

2

OD2

0

OD2

1

OD2

2

SDataIn

IDN

2

ID0

0

ID0

1

ID0

2

ID1

0

ID1

1

ID1

2

ID2

0

ID2

1

ID2

2

Drive

Drive 0

Drive 1

Drive 2

 

The following signal mapping is established between SPI and SGPIO signals.

SPI signals

SGPIO signals

SCLK

SClock

MOSI

SDataOut

MISO

SDataIn

SS

SLoad

 

  • SGPIO Target

Summary:

The SGPIO Initiator implementation is very similar to the SPI Master when using the submode – TI (Start Coincides), which generates a pulse on the beginning of every word. If using a frame with 4 drives (or 12-bit frame), there is no need to even use the Smart I/O.

If more than 4 drives is needed, the Smart I/O can be used to generate the SLoad signal based on the SPI.SS signal.

SPI Config:

Mode: Slave

Sub mode: Motorola

SCLK mode: CPHA = 0, CPOL = 0

Data rate (kbps): 1000

Bit order: LSB first

Rx/Tx data width: Depends on number of drives. It is usually 12 or 16-bits.

SS polarity: Active high

SPI time diagram

SmartIOandSPIII.PNG

SGPIO time diagram

SmartIOandSPIIII.PNG

 

Smart I/O Config:

Data unit:

Input: LUT5 (reset) / 1’b1 (enable)

Opcode: Increment and wrap

DATA0: Constant 0

DATA1: DATA Register

Register value: 255

Size: 8-bit size/width operand

LUT0:

Input: I/O 0 (SGPIO.SDataOut)

Mode: Combinational output

Logic: Input = Output

Output: Chip 0 (SPI.mosi)

 

LUT1:

Input: Chip 1 (SPI.miso)

Mode: Sequential (gated) output

Logic: Input = Output

Output: I/O 1 (SGPIO.SDataIn)

 

LUT2:

Input: I/O 2 (SGPIO.SClock)

Mode: Combinational output

Logic: Input = Output

Output: Chip 2 (SPI.sck)

 

LUT3:

Input: I/O 3 (SGPIO.SLoad) / LUT6 / LUT5

Mode: Sequential (gated) output

Logic: Asserts the SPI.ss based on SGPIO.SLoad and if SPI.clk is toggling

Output: Chip 3 (SPI.ss)

 

LUT4:

Input: LUT2 (SPI.clk)

Mode: Sequential (gated) output

Logic: Delay SPI.clk

Output: None

 

LUT5:

Input: LUT2 (SPI.clk) / LUT4 (Delay SPI.clk)

Mode: Sequential (gated) output

Logic: Detect a falling edge on SPI.clk

Output: None

 

LUT6:

Input: DU / LUT3 (SPI.ss) / LUT5

Mode: Sequential (gated) output

Logic: Asserts when SPI.clk is running

Output: None

 

Clock:

Same clock as the SPI

 

Example:

You can find an example of an SGPIO Target implementation using SPI + Smart I/O here:

https://github.com/Infineon/mtb-example-psoc6-smartio-sgpio-target

 

  • SGPIO Initiator

 Summary:

The SGPIO Initiator implementation is very similar to the SPI Master when using the submode – TI (Start Coincides), which generates a pulse on the beginning of every word. If using a frame with 4 drives (or 12-bit frame), there is no need to even use the Smart I/O.

If more than 4 drives is needed, the Smart I/O can be used to generate the SLoad signal based on the SPI.SS signal.

Example:

The example that shows the SGPIO Target implementation uses the SGPIO Initiator (without Smart I/O). If you need an example of the SGPIO Initiator that supports more than 4 drives, please contact Infineon or leave a message in this blog post.

 

Management Data Input/Output (MDIO)

The MDIO is a PHY management interface to read and write the PHY control and status registers. The interface has two signals:

  • MDIO interface clock (MDC): clock driven by the MDIO Host
  • MDIO data: bidirectional, where the MDIO host and MDIO interface might drive the bus, depending if it is a read or write frame

The MDIO frame has the following format:

PREamble

Start bits

Operation bits

PHYADR

DEVTYPE

TA

ADDR/DATA

32 bits

2 bits

2 bits

5 bits

5 bits

2 bits

16-bits

All 1s

0 0

0 0: Addr

0 1: Write

1 1: Read

1 0: Read+Addr

0x00

to 0x1F

0x0: Reserved

0x1: PMD/PMA

0x2: WIS

0x3: PCS

0x4: PHY XS

0x5: DTE XS

W: 1 0

R : Z 0

Any 16-bit value

 

The following signal mapping is established between SPI and MDIO signals.

SPI signals

I2S signals

SCLK

MDC

MOSI

MDIO

MISO

MDIO

SS

Not used

 

  • MDIO host

Summary:

When using the SPI to implement the MDIO host, you have to short externally the MOSI and MISO lines. When sending a whole frame, you need to write 4 words to the SPI TX FIFO:

1)        0xFFFF (first preamble word)

2)        0xFFFF (second preamble word)

3)        Write: 0xXXXX (00 + 00 or 01 + PHYADR +  DEVTYPE + 10

Read: 0xXXZZ (00 + 11 or 10 + PHYADR + DEVTYPE + 11

4)        Write: 0xXXXX (the address or data value)

Read: 0xFFFF (dummy word)

The usage of the Smart I/O is optional when implementing the MDIO host.

SPI Config:

Mode: Master

Sub mode: Motorola

SCLK mode: CPHA = 0, CPOL = 0

Data rate (kbps): 4000

Bit order: MSB first

Enable MISO late sampling: true

Rx/Tx data width: 16-bits

SS polarity: Active high

SPI time diagram for MDIO Write or Address frame

SmartIOandSPIIIII.PNG

SPI time diagram for MDIO Read or Read+Address frame

SmartIOandSPIIIIII.PNG

Smart I/O Config:

The Smart I/O usage is optional to implement the MDIO host. It might be used to add some delays in the signal to conform with the MDIO specification, if required.

Example:

There is no example available to demonstrate the MDIO host with SPI. If you are interested to find a solution for the MDIO host with SPI + Smart I/O, please contact Infineon or leave a message in this blog post. If you can use a PSoC with UDBs, you can find the MDIO host implementation with UDBs in this post:

https://community.infineon.com/t5/Resource-Library/MDIO-Interface-Component-for-PSoC-6/ta-p/250038

 

  • MDIO interface (slave)

 Summary:

We recommend use the UDBs to implement the MDIO interface. It is not possible to use SPI + Smart I/O to implement a fully functional MDIO interface. You can find the MDIO interface UDB implementation in this post.

https://community.infineon.com/t5/Resource-Library/MDIO-Interface-Component-for-PSoC-6/ta-p/250038

 

List of PSoCs that has the Smart I/O


As we conclude this exploration, remember that the power to innovate lies within each of us. With products like PSoCTM and its incredible Smart I/O block at our disposal, we have the means to create new digital interfaces that were unthinkable. So, go forth, my friends, and let your creativity soar as you embark on your own ventures in the captivating realm of PSoCTM and Smart I/O. The possibilities are endless, and the future is in your hands.

Happy tinkering, and until our paths cross again in the vast world of technology, keep pushing the boundaries and unlocking new frontiers! 😉

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