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How to secure device reliability for SiC-specific degradation mechanisms

Paul_Salmen
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How to secure device reliability for SiC-specific degradation mechanisms

One of the main tasks during the development of an inverter is predicting the lifetime of the device. Therefore, it is necessary to have sufficient models and information available.

While SiC MOSFETs have numerous advantages like higher power density, reduced switching losses, and a reduction of components due to their higher switching frequencies, there is a degradation mechanism called “switching-induced VGS,th drift” that occurs under bipolar AC gate stress including < 0 V.

Literature focuses on DC-BTI drifts and gate-oxide breakdown. However, this does not provide enough information to reliably determine the device lifetime.

In this video, Dr. Paul Salmen, Senior Staff Quality Engineer SiC, will explain a stress test procedure to determine worst-case EoAP parameter drifts under realistic, application-oriented switching conditions to provide a reliable model for prediction, the Alternating Current - High Temperature Gate-Bias Stress (AC-HTGs).

 

Find out more at www.infineon.com/sic-mosfet

 

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