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An increase in portability with PSoC™ 6 software development

An increase in portability with PSoC™ 6 software development

ClarkJarvis
Employee
Employee
25 likes received 5 solutions authored 10 replies posted

Using the ModusToolbox™ Hardware Abstraction Layer (HAL) on the Cortex®-M0+ core of the dual core PSoC™ 6 devices

Several of the ModusToolbox software repositories available on https://github.com/Infineon/modustoolbox-software were recently updated.  One of these updates included a new release of the PSoC™ 6 Hardware Abstraction Layer package (mtb-hal-cat1).  The ModusToolbox™ HAL CAT1 library provides a set of APIs to initialize, configure, and use the PSoC™ 6 MCU resources with a defined hardware abstraction layer.  Utilizing these APIs makes it easier to port applications across devices that support this HAL library and allows you to more easily leverage middleware and libraries that have been developed using these HAL APIs.

Prior to this most recent release, these HAL APIs where only available for use on the Cortex®-M4 core of the PSoC™ 6 devices.  The ModusToolbox™ HAL CAT1 v2.1.0 extends these APIs for use on the Cortex®-CM0+ core.

 

In this blog article, we’ll go through a step-by-step exercise in getting a CM0+ project reconfigured with HAL APIs enabled.  We’ll then take an existing HAL-based project that was originally created for the CM4 core and run it on the CM0+ core.

To illustrate these steps, I’ll be using Visual Studio Code to compile and debug the application and will also be using tools like the project creator and library manager from the ModusToolbox™ v2.4 installation.  These steps will be very similar to the steps that could be completed using the Eclipse IDE for ModusToolbox™, and the general concepts can also be extended to IAR Embedded Workbench or Keil µVision.

 

Getting Started

 

We need to start off with a functional Cortex®-M0+ application.  Within the current release of ModusToolbox v2.4 the easiest way to accomplish this is to use one of the available Dual-CPU code examples.  We’ll then repurpose this as a standalone CM0+ project.

Using the ModusToolbox™ project creator, I’ve selected the BSP for the PSoC™ 62S2 Wi-Fi BT Pioneer Kit (CY8CKIT-062S2-43012).  Next, I’ve chosen the Target IDE as Microsoft Visual Studio Code and have selected the Dual-CPU Empty PSoC6 App from the Getting Started category, as shown in the image below.

ClarkJarvis_0-1650892353370.png

 

Selecting the Create action will clone the code example from the Infineon GitHub repository and create a Microsoft Visual Studio project in the selected application root path directory.

 

 

Updating the ModusToolbox Code Example with the latest BSP and Libraries

 

As covered in the introduction, the ability to utilize the HAL library on the Cortex®-M0+ core requires using the latest version of mtb-hal-cat.  Our next step will be to use the ModusToolbox™ library manager to ensure we have the correct version of HAL associated to our project.

Launching the ModusToolbox™ library manager and browsing to the specific cm0p_app subdirectory of the application, I can see that the current project is referencing an older version of the BSP.

ClarkJarvis_1-1650892353377.png

 

By selecting the existing 2.3.0 BSP release version, a drop down will appear allowing us to select the newer v3.0.0 release.  This 3.0.0 BSP release includes a number of updates and dependencies, including a dependency on the mtb-hal-cat1 library, that will cause the library manager to also pick up the latest 2.x release of the HAL library. 

We can confirm the correct v2.1.0 release of the mtb-hal-cat1 library is included from the Libraries tab.

ClarkJarvis_2-1650892353382.png

 

Selecting the Update action will allow our CM0+ project to be updated with the necessary libraries.

 

 

Modifying the CM0+ project Makefile to support HAL

 

With our project now updated, I’ll open the CM0+ workspace in Visual Studio Code, by browsing to and opening the Dual-CPU_Empty_PSoC6_App.cmop_app.code-workspace file.  The ModusToolbox build system uses make files to configure the various source libraries, toolchains, and assorted variables.  There are a few modifications we’ll need to make to be able to use the HAL APIs in our CM0+ application.

Inside our project directory is documentation specific to the selected CY8CKIT-062S2-43012 BSP.  You can reference this documentation from the …/libs/TARGET_CY8CKIT-062S2-43012/doc directory or from the online BSP repository https://github.com/Infineon/TARGET_CY8CKIT-062S2-43012/blob/master/README.md

This document highlights some of the default BSP configuration COMPONENT and DEFINE values, specifically the BSP_DESIGN_MODUS component and the CY_USING_HAL define.  These values are originally configured within the CM4 project’s Makefile, so we’ll need to add them to our CM0+ project’s Makefile.

In addition to the two default configuration values detailed in the BSP documentation, there is one additional DEFINE that we need to make that is unique to the CM0+.  The HAL defaults to an interrupt priority level of 7.  However, according to the Technical Reference Manual for the PSoC 62 device we are using, the ISR priority level for the CM0+ core can not be greater that 3. 

This is a temporary workaround, that will be corrected a future release of the mtb-hal-cat1 library.  To address this issue in our project, we need to also add CYHAL_ISR_PRIORITY_DEFAULT=3 to the list of additional defines in our Makefile.

Opening the CM0+ project’s Makefile in the VS Code editor, I’ve make the following edits (underlined in yellow):

ClarkJarvis_3-1650892353383.png

 

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Editing the linker script to expand the allowable flash footprint of the CM0+ project

 

The default dual core project that we began with assigned the bulk of the PSoC 62 flash to the CM4 project, and only configured a minimal amount for the CM0+ core.   We’ll need to edit the linker script file to expand the available flash allowable on the CM0+ side.

The available linker script files can be found within the directory structure of the BSP folder for our project.

Since I’m using the Arm GCC Toolchain within the VS Code editor, I’ll need to edit the linker script found in the …/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/ directory as highlighted in the image below.

 

ClarkJarvis_5-1650892353386.png

 

 

The original flash size allowed for the CM0 application was 0x2000 (8KB), as shown in the screenshot below, I’ve increase this to 0x10000 (64KB).  We way we have room to add some meaningful application code.

ClarkJarvis_6-1650892353388.png

 

For this example, I intend to showcase using only the CM0.  If you intend to treat this as a full dual core application, with code being executed on the CM4 side as well, you need to align the linker script for the CM4 as well.   For illustrative purposes, I’ve included an image of the edits that could be made to align the CM4 linker script with the edits we made to the CM0+ project.

ClarkJarvis_7-1650892353390.png

 

 

Writing a CM0+ application with HAL APIs

Our project is now configured to develop an application with HAL.  We’ve updated to the latest HAL library, modified the Makefile to properly compile for HAL usage, and expanded our available flash footprint.

In general, to leverage HAL, one would simply need to add #include “cyhal.h” to the top of the project.

You may also consider the following header files to leverage various defines and definitions.

 

#include "cy_result.h"
#include "cybsp_types.h"

 

We can also utilize the ModusToolbox™ library manager to add any additional libraries to our CM0+ application.

 

I’ll be treating this example as a single core example, with code only executing on the CM0+ core.  If you where to implement a dual core example, there are other considerations to be aware of...  Which core will be initializing the BSP, configuring clock as such.  Additionally, as both cores are potentially leveraging HAL, caution should be used in how the APIs are used and resources assigned to various drivers and peripheral instances.  Consider using IPC to help maintain coordination between cores.

As I’m using only the CM0 core (the CM4 core will not even be enabled), I can add everything to the CM0+ project.

To make this simple, and the further illustrate the portability of the HAL APIs across the different cores, I’m going to replace the existing main.c file entirely with a main.c file from a CM4 code example.

The mtb-example-psoc6-hello-world is a great demo to use here.  Despite being a simple “hello world” demo, there is quite a lot going on as it relates to the HAL APIs.  There are printf’s being generated using the cy_retarget_io library that is implemented using the HAL UART driver.  There are LEDs being toggled using the GPIO HAL driver. Finally, there is a Timer with a registered interrupt callback function implemented with the Timer HAL driver.

To update my CM0+ project, I’ll simply copy the code from the main.c file within the Infineon GitHub repository, and paste this into my VS Code project, replacing the content of the original main.c file.

Because our CM0+ project now utilizes the cy_retarget_io library, we need to add this to our application.  I’ll use the ModusToolbox™ library manager to complete this step.  From VS Code Editor, I can use the Toolbar to select Terminal -> Run Task… menu and chose Tool: Library Manager

ClarkJarvis_8-1650892353393.png

 

Within the Libraries tab of the library manager, I’ll place a checkmark next to the retarget-io and select Update to add the files to my project.

 

Returning to the VS Code editor, I can build and debug my application on the PSoC 62S2 Pioneer Kit, seeing the expected behavior in the terminal window. 

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