Dear Sir,
In Asymmetrical Half-Bridge, Hybrid Flyback, how can we optimal current dip design of high frequency by XDPS2221?
Hi @KUOWENYUNG ,
Maybe you want an ultrahigh power density application for PD 240W at 1MHz，in 1us switching cycles, the dead time between the high side and lower side switches in AHB topologies becomes critical.
According to the paper you mentioned, in the dead time (t2~t3 and t4~t5), or in other words, the ZVS transition period, the current dip occurs to the resonant current iLr, which due to the current shared by the primary and secondary parasitic capacitors, iLr ringing amplitude is affected by the ratio Cps/Coss.
In these two short time intervals, you must not only ensure the fast charging/discharging of Coss to achieve Q1&Q2's soft switch, but also choose the appropriate Cps/Coss ratio to contribute the lowest total power loss. A wonderful derivation is made in the paper, illustrated it below:
Although the operating frequencies are different, the conclusion of the paper is applicable to the HBF topology based on Infineon's XDP platform, in order to achieve current dip optimization, you must meet the following items:
- The parasitic parameters of the primary/secondary switches should be as small as possible. Infineon provides leading power switch solutions for USB PD application:
CoolMOS™ PFD7 or CoolGaN™ Integrated Power Stage (IPS) for primary side:
https://www.infineon.com/cms/en/product/power/mosfet/n-channel/500v-950v/600v-coolmos-pfd7/
OptiMOS™ PD for secondary side:
- Cps/Coss=2.87 derived from the paper may not be the best choice for your application, since it's based on the constant Cps & Coss, as you know, in the real world, they are functions of Vds, combined with the parameters of transformer and resonant capacitor, simulation and iteration should be performed for the optical design.
Operate at MHz frequency in PD application is a tremendous challenge, expensive magnetic materials can easily lead to the costs out of control, we recommend you use a proven low-frequency solution, Infineon already released the 140 W USB-PD reference board with PFC +hybrid flyback combo IC XDP™ XDPS2221, more detail please refer to the following URL:
Regards.
Neo
Dear Neo,
thank you for your suggestion.
I just seem from web side paper, and Q2 is low side switch.
Hi @KUOWENYUNG ,
Let me answer the question about output power first.
If you only care about the HFB power stage， I can directly quote the data from the Infineon's "DEMO_XDPS2201_65W1" engineering report, illustrate it below:
As shown above, the efficiency trend increases as the output voltage /current increase. Although this is measured form the XDPS2201, it is also applicable for XDPS2221.
Please note that above analysis only applicable for the HFB power stage, the combo IC XDPS2221 employs a PFC function block, the overall efficiency performance will not be known until the 140W reference design is released (96.8% peak efficiency as far as I know, released before 2022/12 according to current schedule), please pay close attention to the updates on Infineon portal.
As for the PD 240W application you mentioned, I believe that this power level can be support by the XDP series IC.
Regards,
Neo
Hi @KUOWENYUNG ,
Maybe you want an ultrahigh power density application for PD 240W at 1MHz，in 1us switching cycles, the dead time between the high side and lower side switches in AHB topologies becomes critical.
According to the paper you mentioned, in the dead time (t2~t3 and t4~t5), or in other words, the ZVS transition period, the current dip occurs to the resonant current iLr, which due to the current shared by the primary and secondary parasitic capacitors, iLr ringing amplitude is affected by the ratio Cps/Coss.
In these two short time intervals, you must not only ensure the fast charging/discharging of Coss to achieve Q1&Q2's soft switch, but also choose the appropriate Cps/Coss ratio to contribute the lowest total power loss. A wonderful derivation is made in the paper, illustrated it below:
Although the operating frequencies are different, the conclusion of the paper is applicable to the HBF topology based on Infineon's XDP platform, in order to achieve current dip optimization, you must meet the following items:
- The parasitic parameters of the primary/secondary switches should be as small as possible. Infineon provides leading power switch solutions for USB PD application:
CoolMOS™ PFD7 or CoolGaN™ Integrated Power Stage (IPS) for primary side:
https://www.infineon.com/cms/en/product/power/mosfet/n-channel/500v-950v/600v-coolmos-pfd7/
OptiMOS™ PD for secondary side:
- Cps/Coss=2.87 derived from the paper may not be the best choice for your application, since it's based on the constant Cps & Coss, as you know, in the real world, they are functions of Vds, combined with the parameters of transformer and resonant capacitor, simulation and iteration should be performed for the optical design.
Operate at MHz frequency in PD application is a tremendous challenge, expensive magnetic materials can easily lead to the costs out of control, we recommend you use a proven low-frequency solution, Infineon already released the 140 W USB-PD reference board with PFC +hybrid flyback combo IC XDP™ XDPS2221, more detail please refer to the following URL:
Regards.
Neo
Hi @KUOWENYUNG ,
Below 150V Vds, GaN does not seem to have advantages over traditional MOSFET, I think their main competitive field should be at the 600V level (PFC+AHB Stages in this case).
Assume you have a discrete PFC circuit with an output voltage of about 400V, turn ratio of transformer is 3, so Vsr ≈400/3=133V, a 150V secondary switch should be selected. The core dynamic parameters comparison is shown below (EPC2033 vs OptiMOS™ PD BSC0402NS):
Although the above comparison is not based on the same test conditions, you can still get an intuition from it. Due to the lower price and availability, I think MOSFETs may be the more suitable option on the secondary side.
Still, it is recommended that you employ these 2 types of switches in your prototype to make a final decision.
Regards,
Neo
