AURIX™ Forum Discussions

[VisiterN]

Hi，everyone.

    when i use overlap function to redirection PSPR:0x80040000 to DSPR:0x70004000 in TC27x，i encounter a problem.The situation is as follows :  i create 'const' type variable A=20 at Core0 ,and create variable B = A + 10, when i start Overlay Core0 . 1 . 2, then use XCP change A value to 25, it's can be changed in DSPR, and get the value A =25 and B = 35 with XCP.

    but if i create 'const' type variable A=20 at Core1,when i start Overlay Core0 . 1 . 2, then use XCP change A value to 25, it's can be changed in DSPR, and get the value A =25 with XCP,but B is not changed and still equal to 30.so i think core1 cant use Overlay function redirect  PSPR to DSPR ，address redirection failure. that's why?

     there is someone know that's why?please give me some suggestion.

     Best Regards!

[DownyK]

Hi 

Can you share your Overlay init code? 

Thanks

[VisiterN]

due to encryption system,i copy a part of code as follows.

OVC1_OSEL.B.SHOVEN0 = 1;

OVC1_OMASK0.B.OMASK = 0xE00;

OVC1_BLK0_OTAR.B.TBASE = 0x2000;

OVC1_BLK0_RABR.B.OMEM = 0;

OVC1_BLK0_RABR.B.OBASE = 0x200;

OVC1_BLK0_RABR.B.OVEN = 0;

SCU_OVCENABLE.U = 0x07;

SCU_OVCCON.U = 0x03050007;

thanks.

[MoD]

I guess this is a problem with cache. If core 1 access the constant in segment 0x8 then the value will be cached all following access to the const will use the value from cache instead of the value from segment 0x8 therefore also no overlay occur in this case.
You can check this when you change segment 0x8 to 0xA (same location but uncached). Otherwise you can clear bit 8 of CPU1_PMA0 register. Then segment 0x8 is no longer used for data cache on CPU1.

[VisiterN]

Firstly, Thank you very much MOD.

I tried to disable dcache , it do work properly.but i need enable dcache to improve  program performance,then i tried to enable dcache and   write  to SCU_OVCCON.B.DCINVAL = 0, but core1 still cant work properly,meanwhile core2 doesnt work properly,why?

look forward to your reply.

best regards!

[dw]

Hi VisiterN, from my understood,  you can change segment 0x8 to 0xA (same location but uncached).   For non-overlayed memory operation, you can use 0x80...... for cached. Do you think is it possible?

[VisiterN]

Thanks for your reply.

I'm tring to change segment 0x8 to 0xA. but i still confused about cache,  i disable DCACHE on  0x8, but i use DSPR redirection address is segment 0x7(0x70004000),why it's not disable DCACHE on 0x7?

 finally, whether or not use segment 0x8 with enable cache to properly config overlay function?

Best Regards!

[dw]

Could you please explain a bit more?  Here is a related post. And below description is in user manual for your reference.

[dw]

Just modified a overlay demo for TC397. It's compiled and read 32 bytes from flash, the LMU 0xB00A0000 is mirrored into the target address Test_Map_Cal_Flash[32], it works.

[VisiterN]

thank you very much.

I wonder if using segment 0x8(enable cache) to config overlay driver properly?there is bit SCU_OVCCON.B.DCINVAL，why not?

best regards

[dw]

Could you please explain a bit more on your question?  Thanks.

[VisiterN]

Thank you very much.

I mean that i can use segment 0xA with overlay function,but i can't use segment 0x8 with overlay funciton,what can i do to use segment 0x8?

Best Regards!

[dw]

In my posted example, when you access Test_Map_Cal_Flash[32] in Pflash, you do access LMU in fact. Test_Map_Cal_Flash[32] is in located into 0x8.

[VisiterN]

Thank you very much.

I know what you mean, but LMU is occupied in my project,so if  i using DSPR  replace LMU  how to config overlay driver properly?

Best Regard!

[dw · Accepted solution]

Hi VisiterN, Please check last posted project by me.

[VisiterN]

Thank you very much dw.

I took a look at your project,overlay driver config with LMU and only core2.in my project,i use target address segment 0x8 , overlay memory  is DSPR,but core1 overlay cant work properly? so could you please give me a project with enable overlay in core0,core1 and core 2 ?

follow code in my project.

OVC0_OSEL.B.SHOVEN0 = 1;

OVC0_OMASK0.B.OMASK = 0xE00;

OVC0_BLK0_OTAR.B.TBASE = 0x2000;

OVC0_BLK0_RABR.B.OMEM = 0;

OVC0_BLK0_RABR.B.OBASE = 0x200;

OVC0_BLK0_RABR.B.OVEN = 0;

OVC1_OSEL.B.SHOVEN0 = 1;

OVC1_OMASK0.B.OMASK = 0xE00;

OVC1_BLK0_OTAR.B.TBASE = 0x2000;

OVC1_BLK0_RABR.B.OMEM = 0;

OVC1_BLK0_RABR.B.OBASE = 0x200;

OVC1_BLK0_RABR.B.OVEN = 0;

OVC2_OSEL.B.SHOVEN0 = 1;

OVC2_OMASK0.B.OMASK = 0xE00;

OVC2_BLK0_OTAR.B.TBASE = 0x2000;

OVC2_BLK0_RABR.B.OMEM = 0;

OVC2_BLK0_RABR.B.OBASE = 0x200;

OVC2_BLK0_RABR.B.OVEN = 0;

SCU_OVCENABLE.U = 0x07;

SCU_OVCCON.U = 0x03050007;