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dongben
Level 4
Level 4
25 sign-ins 10 replies posted 10 questions asked

请问tc397芯片的预取指令功能会预取多少字节的pflash?如果它因为预取指令而取到超出我的程序范围的pflash会怎样?

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harvis
Level 5
Level 5
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可以用些机制限制访问空间,比如用MPU限制对pflash空间的访问权限。也可以弄个demo测试一下你的担忧点,看看会出现什么异常。

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Di_W
Moderator
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1000 replies posted 250 solutions authored 100 likes received

TC397芯片的程序Flash接口(PFI)负责将PFLASH存储器与CPU之间连接起来。PFI具有点对点的快速连接,连接到CPU并提供与PFRWB(Program Flash Read/Write Buffer)之间的接口。此外,PFI包含用于存储推测性数据的预取缓冲区。在User Manual提供的信息中,并未具体说明PFI的预取指令功能会预取多少字节的PFLASH。

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harvis
Level 5
Level 5
10 solutions authored First like received First like given

预取指令一次最多取多少个字节的指令取决于TC397 instruction cache line size的大小。

dongben
Level 4
Level 4
25 sign-ins 10 replies posted 10 questions asked

手册上显示cache line size是256bits (即0x20 bytes)。如果我烧录的代码地址是0xA000 0000 - 0xA000 0010,0xA000 0010之后的pflash都是空的,那当cpu在执行0xA000 0000地址上的指令时,这个预取指令功能会把整个0xA000 0000 - 0xA000 001F上的内容全都读出来,当它在读到0xA000 0011这个地址是不是就会出问题?

dongben_0-1700791183108.png

 

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harvis
Level 5
Level 5
10 solutions authored First like received First like given

不会有问题。cache有个命中的逻辑,没命中的chache会舍弃掉的。如果遇到远距离跳转的指令,也会导致cache里面缓存的指令用不到。

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dongben
Level 4
Level 4
25 sign-ins 10 replies posted 10 questions asked

我明白你意思。但是我的问题是说cache在预取指令时,取了我程序之外的pflash会怎样。比如我程序一共才10个字节,我pflash里面那也就这10个字节有有效内容,cache工作时取20个字节pflash存起来以备cpu访问,但是取20个字节这个行为本身超出了我这个10字节程序范围,会不会有问题

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harvis
Level 5
Level 5
10 solutions authored First like received First like given

可以用些机制限制访问空间,比如用MPU限制对pflash空间的访问权限。也可以弄个demo测试一下你的担忧点,看看会出现什么异常。

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Di_W
Moderator
Moderator
Moderator
1000 replies posted 250 solutions authored 100 likes received

在设计时都会考虑到这些。


@dongben wrote:

我明白你意思。但是我的问题是说cache在预取指令时,取了我程序之外的pflash会怎样。比如我程序一共才10个字节,我pflash里面那也就这10个字节有有效内容,cache工作时取20个字节pflash存起来以备cpu访问,但是取20个字节这个行为本身超出了我这个10字节程序范围,会不会有问题


 

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Di_W
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1000 replies posted 250 solutions authored 100 likes received

A cache stores a subset of the main memory in temporary storage spaces called cache lines. Each cache line has a tag that describes its current contents and the address it maps to. Typically, a cache line holds a copy of the current content of memory, allowing the CPU to access data without waiting. The data requested by the CPU may or may not be in the cache. If the requested cacheable data is not in the cache, a cache miss event occurs. In this case, a read operation is performed on the main memory at the correct address, and the data is provided to both the cache and the CPU.

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