AURIX™ Forum Discussions

[User16898]

Hi,
I'm currently trying to configure standby mode,
the first step of entering to standby mode is to turn off peripheral modules clocks via CLC.DISR register.

my code is following:
[HTML]
Ifx_SCU* scu = &MODULE_SCU;
Ifx_QSPI* qspi_module = &MODULE_QSPI0;
Ifx_ASCLIN* asclin_module = &MODULE_ASCLIN0;
Ifx_CAN* can_module = &MODULE_CAN;
Ifx_GTM* gtm_module = &MODULE_GTM;

qspi_module->CLC.B.DISR = 1;
asclin_module->CLC.B.DISR = 1;
can_module->CLC.B.DISR = 1;
gtm_module->CLC.B.DISR = 1;[/HTML]

the problem is that when program execute the first line (qspi_module->CLC.B.DISR = 1)
_trapbus() occure

I'm sure that there is no jobs( like DMA) that are running in background.

why is this happennig if, according to DS this should be the first step to prepare MCU to enter standby mode ?
MCU used is Tc222L

[cwunder]

When you write to a register you need to check its write access rights. The CLC register write access requires you to be in supervisor mode, access protection allowed for this master and you have cleared the CPU Endinit (SV, E, P). See Table 20-2 in the TC23x_tc22x_um_v1.1.pdf.

You are getting the trap because you don't have write access to the CLC register.

[User16898]

cwunder wrote:
When you write to a register you need to check its write access rights. The CLC register write access requires you to be in supervisor mode, access protection allowed for this master and you have cleared the CPU Endinit (SV, E, P). See Table 20-2 in the TC23x_tc22x_um_v1.1.pdf.

You are getting the trap because you don't have write access to the CLC register.

You says I need to be in supervisor mode but user manual says nothing about how to enter this mode.
The table you provided contains only read and hardware read bits, how do I set this access bit then ?

[cwunder]

It seems the "access terms" table is not in the TC22x user's manual. This table is defined in the other user's manuals like on the TC27x-D User's Manual. download this and search for "access terms" and you will find the table on page 1-4.

The CLC (Clock control) registers are critical functions to the system and therefore are ENDINIT protected. To open/close access to ENDINIT write protection you can find this information in the Watchdog section of the User's Manual.

Each CPUx watchdog timer also incorporates a local CPUx_Endinit feature which provides temporal protection against unintended writes to critical local CPU registers and also some system registers which require protection but are not already covered by the Safety ENDINIT.

You can use the iLLD access functions or create your own. Here is an example to enable the CLC clock for the GPT12

    uint16_t cpuWdtPassword = IfxScuWdt_getCpuWatchdogPassword();

    IfxScuWdt_clearCpuEndinit(cpuWdtPassword);
    GPT120_CLC.U = 0; /* enable peripheral and allow sleep mode */
    (void) GPT120_CLC.U;
    IfxScuWdt_setCpuEndinit(cpuWdtPassword);