AURIX™ Forum Discussions

[User19977]

Hi there,

I am using Infineon MCAL and TC275. the spi signals are aligned with 32-bit word. there was a pause of clock before the last word was on the bus.

I have to use ‘CS_VIA_PERIPHERAL_ENGINE’ because I need to insert a large cs-to-clock delay. I know I won't have the issue if using 'CS_VIA_GPIO'.

How to work-around?

Thanks, Ke

[NeMa_4793301]

I don't think there is a workaround, because of the way the TC2xx QSPI peripheral works.

With CS_VIA_PERIPHERAL_ENGINE (i.e., QSPI internal handling of CS), to send 8 bytes, you have to send 7, set BACON.LAST, and then send the last word. The gap you're seeing is the delay in the CPU handling the interrupt.

You can get this to shrink to almost nothing if you use 3 DMA transaction sets instead of relying on the CPU, but even DMA can have a couple hundred nanoseconds of latency.

In TC3xx hardware, QSPI supports a new Move Counter mode that activates CS, sends bytes, and then deactivates CS, without the little two-step shuffle that is necessary in TC2xx.

[User19977]

Thanks for your help.

which interrupt is to handle the BACON.LAST? I am thinking to raise the priority. And how to config the MCAL to use the '3 DMA transaction'?

Thanks, Ke

[NeMa_4793301]

The interrupt function in the MCAL SPI driver is Spi_IsrDmaQspiTx.

The MCAL doesn't support using a DMA linked list. You would have to craft your own complex driver.