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cross mob
Not applicable
in the define:
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) void __interrupt(prio) __vector_table(vectabNum) isr(void)

what is the "vectabNum"?

thank you,
Charlie
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8 Replies
Darren_Galpin
Employee
Employee
First solution authored First like received
It is the vector table - there is one for each core.
Not applicable
Thank you. Is there any problem with just having one table and letting the SRN assignments handle who does what? Or should I have a copy for each core?
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NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
I recommend a separate copy for each core. A best practice for applications is to define an undefined interrupt handler for every vector. If something goes wrong in your setup, you'll find out right away. That will also catch soft errors within the Interrupt Router.
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Thanks, I will give it a try. Just to be clear, each core's table would only contain entries that that core would respond to? In other words, all 3 tables would be different?
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NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
Ideally yes - every core's BIV should be unique, and the entries within that BIV should be specific to each core.

You can live life on the edge and use a common interrupt vector table for all cores, but in my experience, that leads to confusion about which core is servicing the interrupt, which then leads to sloppily handled global variables across cores, which leads to chaos. Proceed at your own risk 😉
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what is a good strategy to keep who does what straight? It looks like it would be possible to have 2 cores assigned to the same uart, for example.
I can imagine a single file where I have all of the interrupt assignment macros in one place instead of spread out over many files. arranged by core and then priority.
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NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
The Interrupt Router only supports one mapping for each request source: that is, each service request goes to either DMA or CPUx. That 1:1 mapping is important for maintaining sanity when debugging a multi-core application.

You have a good imagination - for applications that use the MCAL, the Irq component configuration gathers everything together into one table for easy configuration. It's a good idea to keep all that in one place to avoid conflicts and make sure your priorities are correct.
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This is good stuff, thanks!
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