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Hi,

I copied this right out of the manual. It should move 1 byte from source ('I') to overwrite the 'n' in the destination. It doesn't. I am in supervisor mode and all access enable bits are set. By default, the CLC is enabled, I believe.
Any help would be much appreciated. I am working with a KIT_AURIX_TC277_TFT

Charlie

uint8 source[100] __at(0x70000000) = "I love sunny days";
uint8 destination[100] __at(0x90000000) = "nothing here";


//------------------------------------------------------------------------------------------------------------------------------------
// see page 14-156 for an example
void set_up_DMA(void)
{

DMA_SADR00 = *source; // data source address
DMA_DADR00 = *destination; // data destination address
// DMA_CHCFGR00 |= (010 << 21); // 010 sets it to 32 bit word defaults to 000 = 8 bit byte
DMA_TSR00 |= (1 << 17); // disable hardware requests
DMA_CHCSR00 |= (1 << 31); // start transfer


}
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teoBits
Employee
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Hello CharlieK,

Please take a look at the code example projects for the DMA module here: DMA_Mem_to_Mem_1, DMA_Linked_List_Mode_1, DMA_ADC_Transfer_1, SPI_DMA_1 and UART_DMA_Transfer_1
these examples also comes with a tutorial, which can be found here: DMA_Mem_to_Mem_1 tutorial, DMA_Linked_List_Mode_1 tutorial, DMA_ADC_Transfer_1 tutorial, SPI_DMA_1 tutorial and UART_DMA_Transfer_1 tutorial

If you are interested in other modules and you want to start programming for AURIX™, you can get the new Integrated Development Environment (IDE) here: AURIX™ Development Studio and get inspired by numerous trainings from here: AURIX™ Trainings.

If you are not familiar with Eclipse based IDE’s checkout the Getting Started guide!

Hope it helps,
teoBits
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cwunder
Employee
Employee
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CharlieK wrote:
Hi,

I copied this right out of the manual. It should move 1 byte from source ('I') to overwrite the 'n' in the destination. It doesn't. I am in supervisor mode and all access enable bits are set. By default, the CLC is enabled, I believe.
Any help would be much appreciated. I am working with a KIT_AURIX_TC277_TFT


The user's manual code only performs one DMA move per software request. I see a few issues with your code.
uint8 source[100] __at(0x70000000) = "I love sunny days";
uint8 destination[100] __at(0x90000000) = "nothing here";


//------------------------------------------------------------------------------------------------------------------------------------
// see page 14-156 for an example
void set_up_DMA(void)
{
DMA_SADR000.U = (uint32)&source; // data source address
DMA_DADR000.U = (uint32)&destination; // data destination address
// DMA_CHCFGR00 |= (010 << 21); // 010 sets it to 32 bit word defaults to 000 = 8 bit byte
DMA_TSR000.U |= (1 << 17); // disable hardware requests
DMA_ADICR000.U = (1 << 3) | (1<<7); // Increment both source and destination addresses
DMA_CHCSR000.U |= (1 << 31); // start transfer
}
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That did it. Thank you, I miss the easy things sometimes and really appreciate a second set of eyes.
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I have a memory to memory transaction working now. I do one byte/transfer and as many transfers as the string is long. This works great.
I am trying to work with the UART now and can only send one transfer of 1 to 16 bytes. There must be a HW handshake setting I am missing. I can't get more than the one transfer to happen.
Any hints on how to map the UART FIFO handshaking to the DMA channel? or a bare metal sample would be great.

Thanks,
Charlie
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works now.

//------------------------------------------------------------------------------------------------------------------------------------
void set_up_DMA_Send_UART0(void)
{

SRC_ASCLIN0TX.B.TOS = 3; // let dma handle it
SRC_ASCLIN0TX.B.SRPN = INTPRIO_ASCLIN0_TX;
SRC_ASCLIN0TX.B.SRE = 1;

Ifx_DMA_CH_ADICR adicr_11 =
{
.B.SMF = 0, // dma_adicrxxx_smf_AddressOffsetIsCHDWx1,
.B.INCS = 1, // dma_adicrxxx_incs_AddressOffsetIsAdded,
.B.DMF = 0, // dma_adicrxxx_dmf_AddressOffsetIsCHDWx1,
.B.INCD = 0, // dma_adicrxxx_incd_AddressOffsetIsSubtracted, don't imcrement destination address, same address for every write to the uart
.B.CBLS = 0, // dma_adicrxxx_cbls_SourceAddress31to0,
.B.CBLD = 0, // dma_adicrxxx_cbld_DestinationAddress31to0,
.B.SHCT = 0, // dma_adicrxxx_shct_MoveOperation,
.B.SCBE = 0, // dma_adicrxxx_scbe_SourceCircularBufferDisabled,
.B.DCBE = 1, // dma_adicrxxx_dcbe_DestinationCircularBufferEnabled,
.B.STAMP = 0, // dma_adicrxxx_stamp_NoAction,
.B.ETRL = 0, // dma_adicrxxx_etrl_NoInterruptOnLostEvent,
.B.WRPSE = 0, // dma_adicrxxx_wrpse_WrapSourceBufferInterruptTriggerDiabled,
.B.WRPDE = 0, // dma_adicrxxx_wrpde_WrapDestinationBufferInterruptTriggerDiabled,
.B.INTCT = 2, // dma_adicrxxx_intct_InterruptChangingTCOUNTandEqualsIRDV,
.B.IRDV = 0, // Interrupt Raise Detect Value
};
DMA_ADICR011.U = adicr_11.U;
}

//---------------------------------------------------------------------------------------------------------
void DMA_Send_UART0(uint16 trel)
{

DMA_SADR011.U = (uint32)&source;
DMA_DADR011.U = (uint32)&ASCLIN0_TXDATA.U;

Ifx_DMA_CH_CHCFGR chcfgr_11 = // see page 14-113
{
.B.TREL = trel, // Transfer Reload Value
.B.BLKM = 0, // dma_chcfgrxxx_blkm_OneTransferHasOneMove, 16 bytes = 4, 8 bytes = 3
.B.RROAT = 0, // dma_chcfgrxxx_rroat_ResetAfterEachTransfer,
.B.CHMODE = 0, // dma_chcfgrxxx_chmode_SingleMode,
.B.CHDW = 0, // dma_chcfgrxxx_chdw_DataBitWidth_8,
.B.PATSEL = 0, // dma_chcfgrxxx_patsel_NoPatternCompareOperation,
.B.PRSEL = 0, // dma_chcfgrxxx_prsel_HardwareRequestSelected,
.B.DMAPRIO = 0, // dma_chcfgrxxx_dmaprio_LowPrioritySelected,
};
DMA_CHCFGR011.U = chcfgr_11.U;
DMA_TSR011.B.ECH = 1; // enable hardware transfer request
DMA_CHCSR011.U |= (1 << 31); // start transfers to complete a transaction
}

//----------------------------------------------------------------------------------------------------------
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