In the default configuration, all cores can access each other's RAM (DSPR in the case of a variable) as well as the common (LMU) RAM areas. It should just be a matter of mapping a volatile variable on core1 and core2 to the location in memory where core0's variable is located.
The location of the variable in RAM will have implications with regard to access time, caching, etc. and this must be considered if using the variable in a data-sharing context.
