iLLD - Software interrupt using General Purpose Service Request - SRC_GPSR

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User18132
Level 1
Level 1
Hello,

I'm using TC264 step BC. Tasking compiler.

I'm about to start using QSPI on more than one module. Two SPI busses. I see the iLLD caters for interrupt service routines within the QSPI module. Because two interrupts, at
different levels would now be using the one interrupt service routine, I need to do something different to avoid conflict.

My intention is to use a software interrupt, triggered by each of two QSPI interrupts and a couple of flags.

It seems the IR (interrupt router) has GPSR (general purpose service requests) which are commonly used as software interrupts. I want to do that.

Q. Is iLLD using any of these these GPSR for it's internal purposes?
Q. Could I choose any of the two groups and four requests in each group for my own purposes?

I'm trying to avoid conflict with anything iLLD may be doing.

I've not seen any examples in the demo's. Are there any examples of a software interrupt?


Regards,


Michael Kearsey
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NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
Hi Michael. When you say "two SPI busses", you mean two separate peripherals (e.g., QSPI0 and QSPI1), correct?

If it's truly two separate peripherals, there is no conflict - each instance of QSPI has its own set of interrupts (SRC_QSPI0TX, SRC_QSPI1TX, etc.). You can extend the iLLD example in this sort of direction::

IfxCpu_Irq_installInterruptHandler(&qspi0TxISR, IFX_INTPRIO_QSPI0_TX);
IfxCpu_Irq_installInterruptHandler(&qspi0RxISR, IFX_INTPRIO_QSPI0_RX);
IfxCpu_Irq_installInterruptHandler(&qspi0ErISR, IFX_INTPRIO_QSPI0_ER);
IfxCpu_Irq_installInterruptHandler(&qspi1TxISR, IFX_INTPRIO_QSPI1_TX);
IfxCpu_Irq_installInterruptHandler(&qspi1RxISR, IFX_INTPRIO_QSPI1_RX);
IfxCpu_Irq_installInterruptHandler(&qspi1ErISR, IFX_INTPRIO_QSPI1_ER);


If what you meant was two separate CPUs handling the same QSPI peripheral with a different slave select, that won't work - the iLLD functions don't have any sort of intra-CPU synchronization.
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