Feb 17, 2022
09:30 PM
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Feb 17, 2022
09:30 PM
Dear,
How are the TDU slices0~2 cascaded to 1x 24 bit counter?
TDU slice0 TDUC.TO_CNT coun for TCS clock source.
TDU slice1 DUC.TO_CNT1 count for TDU slice0 carry signal
TDU slice2 DUC.TO_CNT2 count for TDU slice1 carry signal
24bit counter occur timeout when TDUC.TO_CNT/TDUC.TO_CNT1/TDUC.TO_CNT2 all larger than TDUV.TOV、TDUV.TOV1、TDUV.TOV2
Solved! Go to Solution.
1 Solution
Feb 27, 2022
11:14 PM
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Feb 27, 2022
11:14 PM
Hello,
Please refer to the section 28.13.3.1 of the Aurix user manual part 2.
Thanks.
1 Reply
Feb 27, 2022
11:14 PM
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Feb 27, 2022
11:14 PM
Hello,
Please refer to the section 28.13.3.1 of the Aurix user manual part 2.
Thanks.