I am trying something which may be using GPIO pins in an unintended way. But currently I am not sure where exactly the limitation is, so I wanted to ask for inputs if and how this could work:
- We have a board with an Aurix TC397 connected with 4 wires to MMIC_A (normally as QSPI Master).
- For debugging purposes we would like to communicate with this MMIC_A but without the AURIX QSPI module (using a different SPI Master which is better integrated in our software environment)
- We do not have hardware access to any SPI lines since there are no signal lines or vias available for soldering on the bottom or top layer. The pins are not exposed.
- Only 4 GPIO lines and the DAP interface from the TC397 are available to us.
The idea is to use the CPU to simply in a while loop read inputs and copy the logic levels to the outputs as fast as possible while maintaining timings necessary for SPI communication.
I tried it with the code Attached (I hope the one files is enough, the rest would be from the Libraries/iLLD)
- System and CPU clock speed to 300MHz (max.). In theory should be enough for sampling 1 to 25MHz signals.
- Initializing Input and Output drivers
- while loop for copying logic levels of 3 inputs to 3 outputs
- 30x loop runs of observing clock input vs. output with oscilloscope
Currently I am testing on a KIT_A2G_TC397_3V3_TFT before testing on the before mentioned board.
30x loop runs of observing clock input vs. output with oscilloscope (also attached), showed that the delay between input and output is higher than expected and that its inconsistent. The rising edge and high time is changing for every loop run so SPI communication is not possible.
I may have to check again if my CPU is actually running at 300MHz but I am not sure yet how.
Is it possible that reading and writing GPIO levels like that is just inappropriate usage and there is an inherent delay?
Kindly asking for suggestions.