AURIX™ Forum Discussions

[Junzheng]

Hi Support,

We have a safety use case which needs to trigger LBIST on TC377, the bit LBISTREQ and LBISTREQRED of register SCU_LBISTCTRL0 set to high under safety endinit protection.

But LBIST will result in unexpected reset and all cores will run out of control, is the condition for executing LBIST not fullfilled? I couldn't loacte the root cause for this issue.

Best Regards.

[DownyK]

Hi junzheng 

Did you check Lbist configuration?

as i know, TC37x Lbist configuration is below 

LBISTCTRL0.PATTERNS = 0x100;

LBISTCTRL2.LENGTH = 0x3D;

with LBISTCTRL1.BODY = 0;

   - LBISTCTRL1 = 0x54000007

   - LBISTCTRL3 = 0x0F132FFA

with LBISTCTRL1.BODY = 1

    - LBISTCTRL1 = 0x5C000007

    - LBISTCTRL3 = 0xCEBD9DD4

[Junzheng]

Hi Downyk,

Thank you for your reply, LBIST configuration for TC377 is matched according to the above screenshot, but on TC377 project board, SBC TLF35584 is not used instead of NXP FS6500, this change will result in LBSIT executing fail? and bit3/bit16/bit28 of register SCU_RSTSTAT are high.

[DownyK]

I think SBC does not matter. 

if your board LBIST is working, MCU should be warm power reset. 

so bit16(PORST) to high is okay, but bit3 (SMU reset) is not good.

so I think before the LBIST run, SMU should be disabled. 

[Junzheng]

On the TC375 development board(mounted TLF35584,provided by Infineon), we could execute LBIST successfully and get result, the same source code was running on TC377 project board which mounted on project specified SBC (NXP6500) and additional electric circuits, LBIST is executed fail.

You means SMU triggers a reset on LBIST runtime?

[DownyK · Accepted solution]

in my opinion and my experience, what type of SBC does not matter. 

because the LBIST sequence is only involved in MCU's internal process. 

and bit3(SMU reset) in RSTSTAT to high means SMU Reset occurs somewhere.

so I recommend that the SMU module be disabled before the LBIST run.