AURIX™ Forum Discussions
in TC38x,Can the local memory unit(LMU) and thre Distributed LMU (DLMU) as a whole LMU to be used in OVC function SAL-TC387QP-160F300S AD
Show Lesswhen try to debug the example project through miniwiggler, it can not work as below:
but memtool can connect the chip :
MCD basic client can also connect the chip and get the information:
the ADS version is 1.9.20 ,DAS version is 8.0, miniwiggler is V3.1, hardware board is designed by other people and can be connected through UDE/pls
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我现在有6路pwm波,A、B、E、F、G、H,这六路pwm需要同时调频移相,我的B、E需要基于A移向,F需要基于E移相,G和H需要基于E移相,但是GTM-TOM模块pwm同时输出并满足移相有两种情况,一种是都基于A去移相,一种是基于前一个通道去移相,一旦我使用第一种,我的F基于A移相就会超过50%,这将导致PWM出现一个周期的高电平的波形,如果使用第二种我又无法满足我的移相标准,请问是否可以混合使用这两种模式,怎么使用?
祝好!
Show Less1.0 On March 19th Infineon Technical Community hosted a conference with the theme "Infineon AURIX ™ TC3xx Automotive Grade Microcontrollers and Typical Modules Tips and Utilization ( CAN-FD, SMU, ADC )" online seminar, details are as follows
If you missed that live broadcast, don't worry, you can click this link to watch it back: AURIX ™ TC3 special live broadcast, detailing automotive-grade microcontrollers and typical module skills and applications
The link to the live class and materials can be downloaded in the attachment
2.0 The broadcast had a total of 206 questions because of the large number of participants, and some of the more representative questions are selected here for a unified response:
- Question: Is the emergency stop output controlled by SMU_CORE? Or is it triggered directly by a fault signal
Answer: It is set by SMU in advance, and the emergency stop will be triggered when the corresponding alarm appears
- Question: Is it possible to reuse the ecology of the upcoming AURIX TC4x series with the TC3x series? Is it possible to describe the porting difficulty?
Answer: some can be reused. The porting difficulty varies from package to package. Specifically look at the TC4xx_COM/TC4xx_STD options.
- Question: What are the main difficulties in the development of high-end automotive MCUs compared to consumer ECUs, and why does it seem like the process is so far behind?
Answer: Based on functional safety design and automotive application oriented design robustness requirements considerations. It will be less aggressive than consumer grade
- Q: Does the FSP pin support the emergency stop function? What is the significance?
Answer: FSP and Emergency Stop can be triggered at the same time, both to report the fault to the external DEVICE and to turn the port output off.
- Question: In which vehicles are the TC3xx series microcontrollers already widely used?
Answer: BYD, Geely, Changan, etc., many new forces are useful
- Question: Doesn't TTCAN and CAN collision and arbitration both send data by preempting the bus? What is the difference based on event or time?
Answer: TTCAN depends on the specific standard definition, since it is timed and there is no arbitration
- Question: For airbag systems, how does the AURIX ™ TC3xx enable fast and accurate trigger decisions?
Answer: This is dependent on the system integrator's design. Once the sensor detects an abnormal acceleration, the actuator is triggered to activate the airbag to eject.
- Question: What is the significance of receiving a prioritized message when there is only one message per moment on the CAN bus?
Answer: We follow the definition of FIFO BUFFTER to understand the specific receipt of how to deal with, the customer according to the ID and content of their own arrangements
Due to space constraints, the full version of the Q &A can also be viewed in the attached Excel
Some questions are too complex to be answered simply, so it is recommended that you can click the green button "Ask a Question" in the upper right corner (if you can't see it, it is recommended that you narrow your browser to 80-90%)
A guide for newbies to ask questions can be found at: Required Reading | Beginner's Guide
3.0 The speakers for this broadcast are senior engineers (CAE) responsible for Infineon's microcontroller Aurix board.
The following is a selection of typical Aurix technical community questions and answers from engineers
@DI_Wang
How to calculate the sample rate for CAN communication?
TC38x CAN01 RX Works abnormally
TC397 CAN most send 30 frames per cycle
MCU: @Jeremy
SMU_Reset_Alarm_1_KIT_TC397_TFT ERROR
EVADC: @Kunqiao_L
Can we do Parallel conversion together for primary and secondary cluster?
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/AURIX-TC3xx-%E9%AB%98%E9%A2%91%E9%97%AE%E7%AD%94%E9%9B%86%E9%94%A6-%E9%99%8420240319%E7%9B%B4%E6%92%AD%E9%97%AE%E9%A2%98%E9%83%A8%E5%88%86%E5%9B%9E%E7%AD%94/td-p/723508
Show LessHello,
Target device is the TC333LP. The Mbist component follows all the principles and instructions written in the AURIXTC3XX_ts_part1_V2.5.1. The initialization process and running the NDT of GANGs 0, 2, 3 gives positive results and is working without any issues. The situation changes when we want to initialize DSPR SRAMS of the CPU0 (DMEM and DMEM1).
Enabling the test mode using the MEMTEST registers results in the bus error. The situation is the same for DMEM and DMEM1 and they use different MEMTEST registers. The initialization was done in compliance with hints given in the Handling of Large DSPR SRAMs chapter in the TC33xEXT_appx_um_v2.0 document - the test mode for them is not running parallelly.
It does not also seem like an access mode issue - the registers change their values to those which are written into them. The autoinitialization is also not running when the test mode is enabled.
What I have found is that the Data Integrity Error in the Scratchpad memory.
How can this issue be addressed? What could be the reason of it?
Hello, I'm trying to set PIN7 'PS' in Port 21 LVDS Pad Control Register on a TC35x target to '0' to choose the 3.3V supply setting. This pin's hardware reset value is '1' so I'm wondering if I can change it on startup via software initialization. So is this pin value changeable via software? Note: The pin direction is set to 'Input' and pin level is 'Low' in the port configurations.
In case the pin value is changeable, I noticed that there are a couple of Access Mode Restrictions (Master enabled in ACCEN and Supervisor Mode and ENDINIT). How can I unlock these access rights for this register?
Thanks in advance.
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After configuring this register (set DIV), RTC interrupts can only enter once, and after deleting this line of code, interrupts can enter normally. What is the problem, please
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according to Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf 10.9.1 To enable TC3XX Clock Monitoring, do I need to configure some registers ?I notice that in "Figure 89 Clock Monitor ", it seems the monitoring function is controlled by some config regs, and some signal line like "pll0momen/tst ". If I need to config some reg, then what is those reg? to config some reg, then what is those reg? If it's not needed, then, does it means that the Clock Monitoring is enabled by default ?
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC3XX-Clock-Monitoring/td-p/722644
Show LessHello
I am making PWM with GTM TOM module.
I am writing the code that applies to TC367 using the GTM_TOM_3_Phase_Inter_PWM_1_KIT_TC275_LK example code
This example code uses TOM1's CH0 through 6 for PWM waveforms.
CH0 is a PWM Master channel, which determines the period of the three-phase top and bottom pwm waveforms generated in the remaining ch1 to 6
It also enables synchronous pwm waveforms to be generated.
I am using the ccu1tc and ccu0tc interrupt signals based on the pwm waveform generated by this ch0(pwm master) to cause the interrupt to occur at the center of the pwm waveform and at the edge.
So that interrupts occur twice in a pwm waveform cycle.
I hope that the ccu1tc, ccu0tc interrupt signal generated in this ch0 will be the trigger signal to start the adc conversion.
Is there a way?
If any engineers know how to do this, please reply. Thank you.
Show LessAfter disable and re-enable TRNG on TC397, the random number sequence read from DATA32 is same over every reset (including power-on reset and reset button). on development kit)
Board: KIT_A2G_TC397_5V_TFT
Initialize code.
NVIC_EnableIRQ(TRNG_IRQn);
TRNG_CTRL = 6;
NVIC_ClearPendingIRQ(TRNG_IRQn);
// Some delay by busy loop
TRNG_CTRL = 2;
// Read TRNG_DATA32
cpsie i
Interrupt handler.
if (TRNG_STAT has FIPS_ERR or WARN) {
TRNG_STAT = 0x0408;
} else if (TRNG_STAT has RDY) {
// Read TRNG_DATA32
}
I record the DATA32 of the first, second, 100th and 200th interrupts. The four numbers are different in one reset cycle. But the first random number is the same in different reset cycle. So is the second, 100th and 200th number. No FIPS_ERR and WARN is reported.
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TRNG-on-TC397-generates-same-random-sequences-over-reset/td-p/722285
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