Hi there,

I'm using Memtool 2021 on TriBoard  with TC233(DAS) and try to connect to Target but there's a pop up window shows up.

The error message is below.

Message from component "IMTMemtool"

CAN't connect to Target

Message from component "Controller0.Core0. Tc2CoreTarglntf"

CAN't connect target!

Message from component "Controller0.Core0. Tc2CoreTarglntf"

Failed to read target state!

The CPU I am using is "Infineon TC233L".

#DAPminiWiggler

#Memtool

Thank you in advance.

Regards!

Hi All 

We have designed a Control unit based on TC275 MCU, and we want to programe it using this tool "KIT_MINIWIGGLER_3_USB", so could you please check if we are using the right pin out for the connector?

Please see attached picture for the Programmer connector on the board.

Thanks 

Basel Tahboub

Hello,

I am new to development with an AURIX MCU and its microarchitecture specialties and would thus have quiet simple questions : What could be all communication paths that be programmed between CPU0, NVM, RAM and peripherals ? Your response would help me understand which of the interim units and modules are more essential bricks than others, in order to study them first / if they are worth studying first as introduction and afterwards focus on additional/complementary functions among DMU, LMU, PFI, FSI, LMU, DMA, PSPR, DSPR, DFRWB, PFRWB, DPI, PMI, etc. I am sorry If it is a so beginner question.

Thanks in advance for your support.

Hi , just beginning with Aurix dev, some experience with C167 and XE167 controllers.

I want to write two small messages to the serialport.  Ended up in the situation that it only works well when inserting a short wait period.

Made some screenshots of source code parts and serial output corresponding the 'good' and 'bad' situation.

Tried quite some things but was not able to solve this problem.   In between these two parts of the message I don't want to wait at all.

And when stepping through with the debugger , I slow so much down that the code works fine ! 😞

Can somebody point me in a direction to solve  this ?

Hi -

Im trying to run this example in the link below. Compiled as is, the behavior is normal, interupt was triggered, ISR executed. https://github.com/Infineon/AURIX_code_examples/tree/master/code_examples/STM_Interrupt_1_KIT_TC397_TFT

However, when I changed the interrupt service provider in file "STM_Interrupt.c" line 93 from "IfxSrc_Tos_cpu0" to "IfxSrc_Tos_cpu2" (I tried other cores as well, same results), the software stopped working, contradicting what Infineon tutorial PPT page 6 is saying - 

can anyone provide any insights as to why changing the service provider broke the program? 

TIA.

Dear AURIX Support team,

I'm working now with CCU6 module on TC234 AURIX TriCore chip.

I've used the CCU6_PWM_Capture in Example repository.

Following the example, we will have an ISR Handle that will detect both Rising and Falling edges of an external PWM signal.

I've keep all the configuration as the example, only change the CC6 module. Particularly, the example uses MODULE_CCU60 and CCU60 channel while I use MODULE_CCU61 and CCU61 channel. The other configurations such as channel mode or interrupt1.source I keep the same as example. However, my code detects both Rising and Falling edges at the same time when it calls the ISR handle.

Do you know where is the problem is? Thank you very much

Best regards,

Thien Bui

Hi,

I am building app using tasking compiler, I am using #pragma pack(1) to avoid structure padding.

but I am facing this error     ctc E209: #pragma pack: invalid number "(1)"

please let me know how to fix this or to suppress this error.

Thanks

g sai srinivas

Hi team,

We are aimed to calculate the overall CPU core performance of AURIX TC397x. Following the AURIX_TC3xx_Architecture document CCNT, ICNT, M1CNT, M2CNT and M3CNT are the performance counter registers, there is NO straight method mentioned to calculate the overall performance of CPU core. How to calculate the CPU core performance(in %) using Performance Counter Registers?

Shall we take the average percentage of these registers to conclude the average performance of CPU cores(in %)?

Help is most appreciated.

Regards,

Samad.

Hi team,

We are working with AURIX TC397x. For ASC (UART) we are having Shell support i.e., series of commands and their callbacks.

Can we use shell for Ethernet peripheral also? We wanted have Ethernet shell which supports series of commands and their callbacks, Is is possible to do this?

Any help on this, is very much appreciated.

Regards,

Shafi.

Hello,

I am trying to get the Standby Controller on a TriBoard TC387 5V to work with the AURIX Development Studio.

For that purpose I took some of the Bifaces Demo Code and tried to include it into the TC387 SCR Project.

The building runs through and the CArray is generated properly (it seems),

but I can't get any pin to toggle.

The routines I use:

Cpu0_Main.c:

[...]

IfxScuWdt_clearSafetyEndinit(IfxScuWdt_getCpuWatchdogPassword());

//P33.0 - P33.7, P33.9 - P33.15 and P34.1 set for SCR use
while (P33_PCSR.B.LCK)
;
P33_PCSR.U = 0xFEFF;
while (P34_PCSR.B.LCK)
;
P34_PCSR.U = 0x0002;

//boot_mode=0 - XRAM not programmed
IfxScr_init(0);
IfxScuWdt_setSafetyEndinit(IfxScuWdt_getCpuWatchdogPassword());

// Write SCR program to XRAM
IfxScr_copyProgram();

IfxScuWdt_clearSafetyEndinit(IfxScuWdt_getCpuWatchdogPassword());

//boot_mode=1 - XRAM programmed
IfxScr_init(1);

IfxScuWdt_setSafetyEndinit(IfxScuWdt_getCpuWatchdogPassword());

while(1)

[...]

SCR/main.c:

#include "registers.h"

#define SCR_ISR __isr;
#define SFR(X) (*(__near volatile uint8_t*)(X))

#define SCR_RTC_RTCON SFR(ADDR_SCR_RTC_CON)

[...]

void togglePinPort0 (uint8_t pin_id)
{
SCR_IO_PAGE = 0; //Switch back to page 0
SCR_P00_OMTR = (1 << pin_id); //alternatively use OMCR Register Output Modifications Clear Register
// SCR_P00_OUT = 0;
}
void delay (void)
{
unsigned long ul = 50000;
while (ul)
{
--ul;
}
}

void main (void)
{
//
// /* SCU module configurations */
// SCR_SCU_PAGE = 1; /* Switch to page 1 */
//// SCR_PMCON1 = 0x7F; /* all functions including OCDS disabled */
// SCR_PMCON1 = 0x59; //enable RTC and disable other modules
// SCR_NMISR = 0x0; //clear all nmi flags
//
// SCR_SCU_PAGE = 0; /* Switch to page 1 */
// SCR_SYSCON0 = 0;
//
// while (SCR_SCU_SR != 0x08)
// ; //wait until TC enters standby mode
//
SCR_SCU_PAGE = 1;
MAIN_vUnlockProtecReg();
SCR_CMCON = 0x20; //close fback = 100MHz
// SCR_CMCON = 0x1C; // 500kHz
MAIN_vlockProtecReg();
//
// SCR_SCU_PAGE = 2;
// /* IO module configurations */
SCR_IO_PAGE = 2; //Switch to page 2
SCR_P00_PDISC = 0x00; // Enable all pads

SCR_IO_PAGE = 1; //Switch to page 1,
// SCR_P00_IOCR0 = 0x80; //P00 pin 0 is output (General-Purpose Push-Pull Output) -> PCx = 10000
// SCR_P00_IOCR1 = 0x80; //P00 pin 1 is output
// SCR_P00_IOCR2 = 0x80; //P00 pin 2 is output (General-Purpose Push-Pull Output) -> PCx = 10000
// SCR_P00_IOCR3 = 0x80; //P00 pin 3 is output
SCR_P00_IOCR4 = 0x80; //P00 pin 4 is output (General-Purpose Push-Pull Output) -> PCx = 10000
SCR_P00_IOCR5 = 0x80; //P00 pin 5 is output
// SCR_P00_IOCR6 = 0x80; //P00 pin 6 is output (General-Purpose Push-Pull Output) -> PCx = 10000
// SCR_P00_IOCR7 = 0x80; //P00 pin 7 is output

uint32_t test = 0;

SCR_IO_PAGE = 0; //Switch to page 0

while (1)
{
test++;
delay();
togglePinPort0(4); // toggle
togglePinPort0(5); // toggle
}
}

SDCC Compilation:

12:29:23 **** Incremental Build of configuration SCR Debug (SDCC) for project TC387_with_SCR_2 ****
make --output-sync -j12 all 
Building file: ../SCR/main.c
Invoking: SDCC Compiler
sdcc --asm-scr -c --model-large -I"C:\Users\xyz\AURIX-v1.9.8-workspace\TC387_with_SCR_2\SCR" --std-sdcc99 --nooverlay --no-peep-return --opt-code-speed  "../SCR/main.c" -o "SCR/main.o"
Finished building: ../SCR/main.c
 
Invoking: SDCC Linker
i51-elf-ld -T"../SCR/scr.ld" --gc-sections -L"C:\Infineon\AURIX-Studio-1.9.8\tools\Compilers\sdcc_421/share/sdcc/lib/large" -lsdcc -lmcs51 -lint -lsdcc -llonglong -llong -lint -lfloat -Map="scr_a2g.map"   ./SCR/main.o   -o  "scr_a2g.elf"
Finished building: scr_a2g.elf
 
Building target: scr_a2g
Invoking: SDCC Object copy CArray
i51-elf-objcopy -O carray --osize 1 --otyp uint8_t --odef "scr_a2g".h --comments --hinc --xtern --olbl scr_xram --closegaps --hstdint  scr_a2g.elf  "scr_a2g".c
Finished building target: scr_a2g
 
cp *.c ../ && cp *.h ../
 

12:29:24 Build Finished. 0 errors, 0 warnings. (took 944ms)

No success at all so far. Do you guys have any idea where/why this might fail?

Best Regards