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AURIX™ Forum Discussions

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User21797
AURIX™
Hi there, Can HW parity check be used in master mode? From iLLD u can config a master ch to use parity check (<IfxQspi_SpiMaster_ChannelConfig>.parity... Show More
Snehal
AURIX™
Hello. I have MC-ISAR_AS422_TC3xx_CD_2.10.0 package but could find manuals for SENT under user manual folder. Where can I get SENT user manuals? Show More
babu99
AURIX™
Hello Everyone, I'm working with TC37x & TC39x controllers and i want to retain the DSPR data over resets. How to modify the DMU_HF_PROCONRAM register... Show More
Roger_Florida
AURIX™
I have an AURIX TFT eval board with a TC397.  I have been following Chapter 21 of the User Manual part 1 to configure the Extended Memory (EMEM). I en... Show More
Ann0323
AURIX™
For MPN: SAK-TC277TP-64F200N DC, 2 OPN and SP# observed.Kindly pls help to explain the different and will it affect functionality?Thanks a lot! Show More
leekings
AURIX™
  Hello. I'm using TC367 Lite Kit and testing "MCMCAN_FD_1_KIT_TC375_LK" sample code. When i try to use this samplecode , flash error was happen. So i... Show More
Shambhu
AURIX™
Hi, I am trying to generate the correctable alarm0[6] in SMU (for example: CPU0 SRAM PCACHE/PSPR single-bit correctable). but it was not generating, t... Show More
Ivelin
AURIX™
Hello community! I wanted to ask if there are some examples of a basic setup for the  microprocessor mentioned in the title. I have the AURIX starter ... Show More
Michael_Krueger
AURIX™
  Hello, I am trying to use Aurix Design Studio to flash and debug a pre-built application that uses the HighTec Compiler tools. Basically I want to u... Show More
André
AURIX™
Hi all, Can some explain me the behaviour of the TC264 when: sub d1, d2 with d2 > d1 For e.g d1 = 0xA d2 = 0xFFFFFF00 The result is 0x10A, but why? BR... Show More
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AURIX™

In this forum you can post your questions, comments and feedback about the 32-bit AURIX™ TriCore™ Microcontroller. The AURIX™ offers the highest scalability in performance, memory & peripherals across application. It is a safe and secure companion chip, meeting both the ISO functional safety standards and EVITA full security standards. Here you can also find the links to the latest board pages, SW and Tools GitHub, trainings, documents and FAQs