AURIX™ Forum Discussions
hi
i'm testing an isr of the STM.
According to the datasheet, the STM has 2 comparators.
but I want to set up the STM interrupt on each core. (tc38x has 4 core)
is it not possible?
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We are using TC332LP micro. Using VECTOR Stack for Can communication statck up.
Any leads ?
For AURIX TC38x, in the datasheet the max CPU frequency is 300MHz as below -
So with this frequency, each instruction execution time will be : 1 / 300 MHz = 3.33 ns. Is this understanding correct?
Otherwise, how to calculate each instruction execution time or MIPS. Here, the motive is to calculate MIPS for particular application.
Regards,
Abhishek
Show LessRef: AP32272_AURIX_Generic_Bootstrap_Loader.pdf
I am referring to the document about CAN Bootstrap Loading (section 3.1.1 – Figure 10) and am not able to find the information regarding Send Command and data (refer to chapter 5).
Below is the Screenshot what I am referring to. Could you please let me know which document does this chapter 5 refers to?
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Can I use SPU to compute 2D or 3D MUSIC or ESPRIT algorithm really fast?
Thank you.
Hi,
In case of global variables, names of the variables are not appearing in generated map file. I have declared global variable as below:
Then used #pragma to route variable to "OS_OsApplication_ASILA_VAR_INIT_SEC" linker section. It is generated in MAP file as below:
|------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| .data.OS_OsApplication_ASILA_VAR (15985) | 0x00000032 | 0x0 | OS_OsApplication_ASILA_VAR_INIT_SEC (23586) |
|------------------------------------------------------------------------------------------------------------------------------------------------------------------|
As seen, the name of variable is not present in this map file entry.
Whereas in some cases, where data is routed to default sections, names of the global variable pop up in the map file. For example, in below snap, variable Tmr_500ms_c0 and Bsw_Core_PostRteStart do appear in generated in data_SEC section map entry.
|------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| .data.CRT._999001_temp (15963) | 0x00000001 | 0x0 | data_SEC (23614) |
| .data.Timer_Core0._999001_Tmr_500ms_c0 (16010) | 0x00000001 | 0x00000004 | |
| .data.Timer_Core1._999001_Tmr_500ms_c1 (16029) | 0x00000001 | 0x00000008 | |
| .data.Timer_Core2._999001_Tmr_500ms_c2 (16046) | 0x00000001 | 0x0000000c | |
| .data.main.Bsw_Core_PostRteStart (23175) | 0x00000004 | 0x00000010 | |
|------------------------------------------------------------------------------------------------------------------------------------------------------------------|
How to enable this by default? I need to generate global variable with names and addresses in map file sections.
Show LessDear Mr. Robert Kearney & Robert Valascho,
Could you please talk about GTM Optimization of Electric Motor Algorithms more detailedly?
Thank you.
Show LessI use hightec tool chain in Aurix development studio by installed hightec free toolchain, and set the corret toolchain path in ADS.
I found that , when i Used the original tasking compiler, the program works fine, but for the hightec toolchain to compile and burn, the program did not work, and the same code is used for both compilations, what should I do to solve it?
Show LessHi,
My company bought TriBoard TC364 for development purpose. Currently we met some DMA issues. HighTec support suggests me to read following 2 documents but I need access requirement. Could you please give me the access right to these 2 documents? Thanks!
- AURIX TC3xx Family: AP32467 - DMA linked list modes
- AURIX TC3xx Family: AP32552 - AURIX TC3xx DMA Double Buffering Mode
Kind regards,
WenHai
Show LessHello,
I was trying to modify the linkerscript after encountering an overflow problem. But I have these errors throw right now
I suspect that while doing my linkerscript changes, some other unwanted characters have been added unintentionally. I can see them when viewing my changes in git but don't know how to git rid of them if it is the cause.
Appreciating if you can help me figure out what is the root cause of these linking err and how to git rid of them.
.lsl is attached as zip file.
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