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AURIX™ Forum Discussions

dongben
AURIX™
tc397如果把cpu0内狗超时的smu alarm ALM8[10]设置为触发NMI trap。那么当cpu0内狗超时时应该触发NMI trap且AEX寄存器的bit9 NMISTS应该置位。但是我测出来的结果是NMI trap能进,但是AEX寄存器的bit9没有被置位。而其它配置成了NMI tr... Show More
Christ0ph
AURIX™
Hello,while having e.g.  AN4 in G0 sampled with channelneigbours e.g. AN2 and AN3 in "continuous mode" as fast as possible, would it be possible to wr... Show More
sanket
AURIX™
Hi, I need to flash customize boot loader in Infineon TC375 MCU, but BootROM memory not having write access to write bootloader. Any idea how to wri... Show More
sri_bendi
AURIX™
When the temperature of the hardware (that is using Aurix 38X) is reduced (temperature is still higher than the value in PMS_DTSLIM), Aurix 38X is get... Show More
Translation_Bot
AURIX™
Recently, when selecting a chip, I need to know the DMPIs for this chip. The search document was not foundsmartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/A... Show More
Translation_Bot
AURIX™
Hello, I have encountered a difficult problem during development, and I hope you can help answer it. The flash register in PMU0 does not have a memory... Show More
Translation_Bot
AURIX™
Hello, the Flash model I am using is S25fl512SAGMFMR10. Now the flash is write-protected, I wanted to remove the write protection in uboot, but it has... Show More
Translation_Bot
AURIX™
Now I want to complete the fault injection through software Safety Mechanism: SRI Error Detection Code (EDC) Alarm: EDC Read Phase Error Alarm Ty... Show More
OliverZhc
AURIX™
I'm trying to set MBABCLR and ZBABCLR in CPUx FLASHCON2 to solve ALM7[26] and ALM7[27], but the address for FLASHCON2 is 32 bits in my case. I tried t... Show More
Jinakot
AURIX™
LBIST
solved msg Solved
I tried to Set SCU_LBISTCTRL0 REGISTER in order Trigger COLD PORST in TC3xx Bellow you can find what I set: PER.Set.simple D:0xF0036164 %Long 0x800000... Show More
Forum Information

AURIX™

In this forum you can post your questions, comments and feedback about the 32-bit AURIX™ TriCore™ Microcontroller. The AURIX™ offers the highest scalability in performance, memory & peripherals across application. It is a safe and secure companion chip, meeting both the ISO functional safety standards and EVITA full security standards. Here you can also find the links to the latest board pages, SW and Tools GitHub, trainings, documents and FAQs