AURIX™ Forum Discussions

HI，expert：

目前我正在进行关于TC334芯片的BootLoader的开发，需要得到英飞凌工程师的相关支持，具体如下：

1.请帮忙评估一下我目前使用官方的板子“KIT_A2G_TC334_LITE”是否适合用于研究BootLoader开发，当然我有购买英飞凌官方的DAP烧录器；

2.能否提供给我关于TC334开发BootLoader的相关资料和源码例程；

以上需要英飞凌工程师的支持，谢谢！

I am working with TC387 controller and observing around 100% CPU load when traffic on CAN bus is increased.

How CAN Traffic is increased-

By sending messages from Canoe at 1ms periodicity irrespective of their configured periodicity as per DBC file.

CAN is configured as Interrupt Based.

Impact of Increased CPU Load-

 CAN communication stopped working due to increased load on Core0.

Communication stack is implemented on Core0.

Core Impacted-

CPU load is reaching peak on Core0 where the CAN messages from COM are received and processed and further shared to other applications.

Other cores are not impacted significantly due to increased CAN traffic.

Query-

What measures can be taken /checked in order to optimize the CPU Load due to CAN traffic increase so that CAN communication remain unaffected?

Hello,

I am currently working on RTOS project involving the TC397XE processor with six cores. I have a specific requirement to calculate the memory usage for each core, including PSPR and DSPR. This information is crucial as it helps me determine if there is any memory overload and whether it is feasible to add more tasks to the system.
Additionally, I would like to assess how much memory my application consumes from the FLASH memory.
I'm also interested in exploring this memory profiling feature for bare metal applications.

Could you kindly provide guidance or a solution for achieving these memory calculations?

Thanks in advance.

Currently, we have encountered a serious problem when using the EVADC of TC367 chip in project development: when configuring the queue input register (QINR) for writing, there will be a problem of losing individual channels after burning the writing board. After each power on, the channels may be lost, and individual channels do not convert. The channels lost are random, and sometimes the channels are not lost after power on, which is a serious problem for product development.
The configuration code of the channel queue is as follows:
(*Qinr). U = 0x00000020; // add channel 0 to the conversion queue
(*Qinr). U = 0x00000021; // add channel 1 to the conversion queue
(*Qinr). U = 0x00000022;
(*Qinr). U = 0x00000023;
(*Qinr). U = 0x00000024;
(*Qinr). U = 0x00000025;
(*Qinr). U = 0x00000026;
(*Qinr). U = 0x00000027;

Is there any relevant writing requirement for writing the Qinr register (such as the requirement that it cannot be written continuously)? I have not seen relevant instructions in the relevant instructions of TC367 documents. Could you please provide relevant instructions or materials?

目前在项目开发时使用TC367芯片的EVADC时遇到了严重的问题：在配置队列输入寄存器(QINR)进行写入时在烧写入板子后会出现个别通道丢失的问题，每次上电后可能会丢失通道，个别通道不进行转换。丢失的通道随机，有时上电不丢失通道，这对于产品开发来说是很严重的问题
配置通道队列代码如下：
（*Qinr）.U = 0x00000020; //将通道0加入转换队列
（*Qinr）.U = 0x00000021; //将通道1加入转换队列
（*Qinr）.U = 0x00000022;
（*Qinr）.U = 0x00000023;
（*Qinr）.U = 0x00000024;
（*Qinr）.U = 0x00000025;
（*Qinr）.U = 0x00000026;
（*Qinr）.U = 0x00000027;

是否对于写入Qinr这个寄存器有相关的写入要求（例如不能连续写入之类的要求）我在目前看到的关于TC367的相关说明文档中没有看到相关的说明。麻烦可以提供下相关的说明或者资料吗

tc397如果把cpu0内狗超时的smu alarm ALM8[10]设置为触发NMI trap。那么当cpu0内狗超时时应该触发NMI trap且AEX寄存器的bit9 NMISTS应该置位。但是我测出来的结果是NMI trap能进，但是AEX寄存器的bit9没有被置位。而其它配置成了NMI trap的alarm产生是能够使AEX的bit9置位的。这是有bug吗？