AURIX™ Forum Discussions
Is there no send output function in the illd library, I didn't find it ,Can you remind me if there's something relevant in the Illd library?If there's no content in the Illd library, can you share some demos?🤔🐌
Show LessDevices: TC387QP, Tasking, Lauterbach
Issue decription: When I use the Cached LMU0 RAM (0x90040000--0x9005FFFF) for DATA/BSS global variables, there are two problems.
1. For DATA ram, if I define an array or a structure in code with initial value like below C code, and there is not a instruction to overwrite the array, but we find that the array can not be copied successfully during the normal operation (usually the innitial vlaue should be copied in _c_init_entry), and I confirmed that the copy table generated by tasking is exactlly right.
C code: volatile float32 Test_Ram[15] = {415.8, 415.8, 415.8, 415.8, 415.8, 415.8, 415.8, 415.8, 415.8, 415.8, 415.8, 415.8, 415.8, 415.8, 415.8};
Trace32 var watch: volatile float32 Test_Ram[15] = {415.8, 415.8, 415.8, 415.8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
2. For BSS ram, if I define a large structure variable in code, and we have a issue that there are some elements of the structure can not be cleared to zero after any reset (like wdg timeout, trace32 in target reset or others). Most elements of the structure can be cleared to zero, but always there are some elements can not be cleared.
Do we have to pay any attentions to the cached memory when we using them?
Show LessI would like to ask for support for the below issue facing with the environment as mentioned below.
Working Environment:
controller- TC277TE
Compiler- Tasking 4.0r2
Debugger- trace32
Requirement: To create a build which should have all code at desired location (not default location) except jump instruction at RESET location.
Issue: Here I am using library for some functionality like- _c_init().But for this library code, I am not able to change the code location to desired location.
Here for your reference, i have attached the source files, LSL file, compiler, linker and map files. Please let us know how can I resolve the issue.
Regards,
Dharmik B Show Less
Hello,
Thank you for providing "Infineon MCU Memory Analyzer" for obtaining MCU memory utilization, which available for TLE, XMC™ and PSoC microcontroller family.
I am requesting you; can you please also provide us same for Aurix™ based microcontroller?
Thanks & Regards,
Prathamesh.
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I am using M1 mac air and would like to develop in Windows 11 environment through Parallels.
Aurix Development Studio was installed without any major problems,
but problems occurred when trying to build and flash.
The build seems to have been completed normally,
but the tools required for Flash do not seem to support ARM Windows properly.
I attached a picture, but since it is a Korean Windows, the error is displayed in Korean.
It is a tas_server.exe problem.
Even during installation, an error message appeared saying that installation can only be done in an x64 environment.
I wonder if there are any plans to support ARM64 Windows.
Show LessHi team, I am trying to run the following example code without any changes on Tc399 triboard EVK: https://www.infineon.com/dgdl/Infineon-ASCLIN_SPI_Master_1_KIT_TC397_TFT-Training-v01_02-EN.pdf?fileId=5546d4627883d7e00178a2d609943911&redirId=136496 As per page 8 of the training document, I should be able to see the data moving into the Rx buffer. However, once the transmission is complete, I can see only "0xFF" in place of both bytes. Is there a reason for this? I have not made any change whatsoever to the code.
Show LessI disabled SCU_RSTCON.SMU =0x0 (No reset is generated for a trigger of SMU).
I configured ALM10[0](Software Alarm 0), ALM10[1](Software Alarm 1) as SMU_RESET. Then set SMU to RUN and set command SMU_Alarm(0).
I observed that ALM10[0] is set to 1, SCU_RSTSTAT.SMU is 0, reset does not occur. I guess this is as expected.
Then I set SCU_RSTCON.SMU to 0x1 (A System Reset is generated for a trigger of SMU reset), and issue command SMU_Alarm(1).
I observed that ALM10[1] is set to 1, but the reset does not occur, which is not expected because I have set SCU_RSTCON.SMU to 0x1.
I paid attention to SE protection and SMU_KYES protection, it should not be their problem.
Can anyone give me some advice?
Why did I set SCU_RSTCON.SMU back to 0x1 and trigger Software Alarm 1 through the SMU command, but the rest did not occur as expected.
Hello,
I am currently working on an ERIKA project for TC27x device. I have a debugger, and I want to load the application directly into RAM memory. So, I made some modifications to the linker script to link sections to PSPR and DSPR. Also, I changed the start address, interrupt table address, and the trap table address. However, I still encounter errors regarding linking the zrodata sections, even though I linked it in the mpe:vtc:abs18 section layout to the DSPR0 memory.
Please find attached the linker scripts (just remove the '.html' at the end of their names).
Thanks in advance.
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