AURIX™ Forum Discussions
I am currently working on DSADC in TC37 microcontroller. Here in the user manual, the following info is mentioned regarding passband frequency.
"Related to hardware characteristic for passband frequency ≤ 10 kHz the FIR1 has to be used with a decimation rate of 1:1." [Source: AURIXTC3XX_um_part2_v2.0 (1) (1).pdf (Page : 1366)]
Is the above passband frequency referring to input analog signal's frequency? Also it is mentioned to use FIR1 filter for passband frequency ≤ 10 kHz. Does anyone the reason for the need to enable FIR1 filter here?
Show LessHi,
初次使用TC375,在使用EVADC时,当输入电压是0时,转换结果是16,应该是没有校准的原因。
请问如何对EVADC进行校准。
谢谢!
Gavin
Hello,
I am trying to increase the CPU lock so first I tried one of the existing examples:
CCU_Clock_1 for KIT_AURIX_TC397_TFT (imported/downloaded directly in Aurix Studio). Here is the link to the example code on github: https://github.com/Infineon/AURIX_code_examples/tree/master/code_examples/CCU_Clock_1_KIT_TC397_TFT
Kit: https://www.infineon.com/cms/en/product/evaluation-boards/kit_a2g_tc397_3v3_tft/
According to the documentation there should be 100MHz clock on P23.1 --> I am only seeing 1MHz
Checked the crystal on the PCB and measured the signal on the XTAL inputs --> 20MHz crystal is connected (as expected from the Kits Datasheet)
I tried changing the N,K,P factors and I can see changes on the output. But there is no way I can achieve 100Mhz or higher like this.
My goal would be to achieve 300MHz CPU clock.
Any ideas why the clock output frequency would be so much lower than expected? I would go on and check each register setting related to the clock but with no expectation to find anything, some guidance would be appreciated.
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Why did I use ARUIX to write FLASHDRIVER, modify the LSL link file according to Tasking, and run the target program in RAM. I can see that the target is on the RAM address in the MAP file, but why does the hex file all start with Flash, and the hex file doesn't output the RAM content I want.
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/ARUIX-HEX-RAM-TASKING-flashdriver/td-p/680298
Show LessBecause I want to create a project that runs on a single core, then when I modified the LSL file of the TC38x project, I deleted the content related to tc0-tc2 and kept only the content of tc3. The compilation found that the default space_id_offset = 400 will report an error. The error message is as follows:
ltc F019: unrecoverable error: caught unknown exception
ltc E100: unexpected error: fatal error caused
make: *** [makefile: 76: TC377_pinmap.elf] error 1
" make --output-sync -j8 all " terminated with exit code 2. Build might be incomplete.
However, if you modify it to space_id_offset = 300, the compilation succeeds.
Excuse me, the description of space_id_offset in lsl's explanation file is:
The address spaces in each imported core must have a unique ID in the link task. With the keyword
space_id_offset you specify for each imported core that space IDs of the imported core start
at a specific offset.
So, what is the exact scope of its settings? Or, what are the rules that indicate how it should be set correctly?
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/lsl%E6%96%87%E4%BB%B6%E4%B8%ADspace-id-offset%E7%9A%84%E5%90%AB%E4%B9%89/td-p/680148
Show LessHello Support,
We have been trying to understand the ESM present in manual AURIX TC3xx Safety Manual v2.0 1.pdf
Please help me to understand this concept so that I get the complete picture before implementing this ESM.
Thanks & Regards,
AF
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