Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob

AURIX™ Forum Discussions

FCB
AURIX™
The UM mentioned that "The lockstep error is reported to the local CPU, which flags the PFLASH read path monitor alarm." But I cannot find any registe... Show More
Anonymous
AURIX™
Hello,I am using TC27x Triboard. when i tried to Flash my Application in Flash0 i am getting a Sequence Error.I am able to write 248 Bytes, but when i... Show More
Translation_Bot
AURIX™
As shown in the figure, when viewing the resource file, an error failed to create an empty document was reported.  smartconx_target@Q!w2e3r4t5y6u7i8... Show More
雪狼
AURIX™
PSDR 和 DSPR
solved msg Solved
PSPR 主要用于放置静态函数,提高函数执行效率 DSPR 主要用于全局变量、现场保护的上下文管理和堆栈等数据 以上是我找到的关于PSPR 和 DSPR 的解释,我有两个问题: 1. PSPR 和 DSPR中的指令或数据需要用户在lsl文件中指定吗 2. 系统运行时的代码和数据都需要载入PSPR 或... Show More
雪狼
AURIX™

在链接文件中,会有bus的定义,例如 map cached (dest=bus:sri, dest_offset=0x80000000, size=1M)

我的疑惑点是,括号中的bus及sri是随意的定义的吗,另外bus在链接文件中有什么用处,谢谢~

yucheng
AURIX™

目前使用TLE7242 需要时钟源,25Mhz时钟源 时钟源来自于TC377的 可以提供时钟的pin 目前因为这条时钟线比较长,故此导致 倍频较高,EMI实验不过

是否可以通过 TC377自身的展频 从而使得输出的 时钟也可以展频

最终通过 EMI 测试

anwar
AURIX™
I’m working on Aurix TC387 microcontroller using IFX Low-Level Driver library (iLLD) version iLLD_1_0_1_17_0. I’m unable to configure I2C pins IfxI2c0... Show More
Anonymous
AURIX™
Hi,everybody,How to deal with the CAN bus errors?such as 'BIT0','BIT1',LLE,LOE,and so on.In additional,what should I do when class A or B trap occurs? Show More
harrechr
AURIX™
Hello, I am trying something which may be using GPIO pins in an unintended way. But currently I am not sure where exactly the limitation is, so I want... Show More
PawLo
AURIX™
Hi EveryoneI try to follow documentation of Tasking Compiler to change linking to be incremental - so far without success.My idea to enable incrementa... Show More
Forum Information

AURIX™

In this forum you can post your questions, comments and feedback about the 32-bit AURIX™ TriCore™ Microcontroller. The AURIX™ offers the highest scalability in performance, memory & peripherals across application. It is a safe and secure companion chip, meeting both the ISO functional safety standards and EVITA full security standards. Here you can also find the links to the latest board pages, SW and Tools GitHub, trainings, documents and FAQs