I am simply imported ASCLIN_UART_1_KIT_TC375_LK project code, complied and flashed. However, I am not seeing "Hello World" message on the Aurix IDE terminal as well as putt. Any suggestion what could be going wrong with my setup?
Thanks in advance!Show Less
I have configured GTM_ATOM0_CH5_CTRL.RST_CCU0 = 1 (Trigger TRIG_), when I set
GTM_ATOM0_CH4_CM0 = GTM_ATOM0_CH5_CM0 = 000186A0 (Frequency Ticks/Counts required for my application) and GTM_ATOM0_CH5_CM1 = 0 (0% duty cycle), I see the PWM output is always commanded high.
I am wondering about this behaviour, my expectation was that the PWM output will be low.
I went through the Section 220.127.116.11.1 of the Reference manual which talks about the behaviour of CNO, CM0 & CM1 when CN0 is reset by the trigger from another channel.
From this section Iwhen CNO is reset (by Trigger TRIG_) it becomes equal to CM1 (0) and should immediately become low.
Could you please clarify what is going on in this case ? Any work-around to overcome this problem ?
Adding another observation, When i keep rest of the configuration same and change GTM_ATOM0_CH5_CTRL.RST_CCU0 = 0 (Matching comparison with CM0), the PWM output becomes low
Below error showing in V6.3r1 in linker file, but same Linker file can build successfully in V6.2r2. let me know if any changes required in linker file to build in V6.3r1.
ToolEnv\0_Build\1_Config\Config_Tricore_Tasking\Lcf_Tasking_Tricore_Tc.lsl" 844/18] LSL unexpected error: could not find heap section heap
ltc F019: unrecoverable error: fatal locate error
amk E452: ["makefile" 119/0] target 'Application.elf' returned exit code 1
amk E451: make stopped
Thanks and Regards
In my application, I have two TC367 controllers on the same PCB (ECU) and QSPI0 from Controller1 is connected to QSPI0 of Controller2. QSPI0 on controller1 shall be configured as MASTER and QSPI0 on controller2 as SLAVE. And I need to establish the communication between two controller via QSPI/DMA.
My requirement is to have around 20~30bytes periodic communication @ 5Mhz baud-rate.
Using QSPI Long Mode and DMA, by enabling QSPI Tx and Rx interrupts to DMA Channels 8, 9. I am triggering Tx in a 1ms periodic runnable by updating the BACON configuration register.
I have a total of 6 x 32-bit buffers as I want to transmit 24bytes as one frame. Master side Tx/Rx seems to be working fine, but the data from Slave has some problem. Among the 6x32-bit buffers, MASTER is receiving correct value for only 1st buffer as shown in the below picture.
It seems DATAENTRY register on SLAVE controller is not getting updated properly via DMA... So, slave is sending all "1". I tried few methods like to update BACONETRY on slave controller within the DMA Transaction complete ISR routine, but nothing seems to be working.. After comparing DMA registers between Controller1 (MASTER) and Controller2(SLAVE), I noticed HTRE bit is flickering between Enabled/Disabled, which doesn't happen on Controller1.
I am attaching my code here. Would someone please provide any suggestions to resolve this issue?
** Please note that I have same software (hex file) running on both controllers. But I differentiate the code in the software for both controllers based on a particular GPIO pins status. If these GPIO pins set to high, it means that is controller #2. When I power-up the ECU, both controllers will startup approximately the same time.
Customer plan adopt TLE9255 at Linux OS, and need to conform SocketCAN.
Have you any available resource getting started?
Dear AURIX Forum members,
My project has TC367v0 MCU embedded and we are using Infineon/TRICORE TC39XX drivers delivered from INFN.
CAN driver version: V10.10.1 AS4.2.2
TX/RX processing type: INTERRUPT
Currently we are facing below issue.
-We have 2 CAN FD Channels and on channel1 CAN1 we have 65 Messages/Frames [50 RX, 15 TX] (41 Application, 3 DIA, 1 XCP, 6 NM frames)
and in Channel2 CAN2 we have 7 Messages/Frames and No TX Frames.
- On channel1 CAN1 Out of 50 RX frames we are getting issue for 3 set of frames where CAN IDs are 1041, 1043,1044 respectively. Randomly and some times often the frame is missing from driver and not notifying to application, this leads to serious customer issues. Missing frames are observed for 1 to 1.2 sec in customer test even though bus load is around 58%.
Please let me know if you face this kind of issues. Any information to fix in driver level is really appreciated. Thank you so much in advance.Show Less
Excuse me, when I click on the lock, the above can not be operated, how should I return to the unlock state, I can operate the above UCB options.
i can't find iLLD for TC337 in aurix development studio or code example in github. Could you help to download iLLD for Aurix TC337.
Thank you very much.