AURIX™ Forum Discussions
Hello,
There is a statement about resolver excitation says that "To implement this functionality into the system, no additional integrated circuits are needed; only the power stages for the S5 and S6 signals and a few other usual passive components are required."on "AURIX™ TC3xx functional safety (FUSA) in a nutshell.pdf"
Is this means that can I directly connect to Excitation Signals to the Resolver?
Please find attached.
BR,
Mehmet
Show LessHi,
Recently, I added OneEye's oscilloscope to my 275 project, using the code example :Infineon AURIX_OneEye_DAS_Oscilloscope_1_KIT_TC275_LK
My original project code and the original code examples work well on their own. After add, the project structure looks like this:
SignalGenerator.c/.h comes from the code example. At this point, the project was working and I was able to get the waveforms I wanted on the OneEye oscilloscope.
I tried to change the file name:
"SignalGenerator.h"-->" VCU_Osci.h"
"SignalGenerator.c"-->" VCU_Osci.c"
In this case, a CPU0 trap was encountered while debugging the program. This didn't happen to the program without changing the filename. CPU1 and CPU2 do not have any user code.
About the trap, The following information is provided in TriCore® TC1.6P &TC1.6E Core Architecture 32-bit Unified Processor Core User Manual (Volume 1).pdf :
Class 2 — Instruction Errors
TIN 4(ALN) - Data Address Alignment
After testing, it was found that the oscilloscope traps when its filename is below VCU_main.h/.c, but not above it. For example, changing the filename to Ocsi.h/.c will not trigger the trap. This appears to be a link error.
How did this happen, and what can I do to avoid it?
The following is a simplified version of the project that still has the errors.
More information can be found at the following links:
Solved: Re: With OneEye's oscilloscope, the oscilloscope c... - Infineon Developer Community
Thanks!
Show LessI want to know the status of the other cores i.e, core 1 and core 2 CPU's are in ideal state or busy state from the core 0.
Is there any possible way to know the status of other cores.
Thank You.
Regards,
Venkat Show Less
Hello,
regarding the ASCLIN module the question came up how to configure it to be used with devices that need SPI mode 0.
If I see it correctly only the clock polarity can be changed, but not the clock phase.
Thus typically the connected slave device would need to understand SPI mode 1 or 2.
Is there a way to change the clock phase?
(Using iLLD)
Best
beamk
After setting SYSPCFG0 to 0 I can't connect to my board.
(Even flash downlad.)
How can I fix this problem.
What is the explanation of MsgObjId, messageid, topMSGID, bottomMSGID for can bus?
g_multican.canMsgObjConfig.msgObjId = (IfxMultican_MsgObjId)currentCanMessageObject;
g_multican.canMsgObjConfig.messageId = g_messageObjectConf[currentCanMessageObject].messageId;
g_multican.canMsgObjConfig.control.topMsgObjId = (2 * currentCanMessageObject) + SRC_EXTENDED_MO_OFFSET;
g_multican.canMsgObjConfig.control.bottomMsgObjId = g_multican.canMsgObjConfig.control.topMsgObjId + 1;
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/%E9%97%9C%E6%96%BCcan-bus-id-%E5%AE%9A%E7%BE%A9%E5%95%8F%E9%A1%8C/td-p/686411
Show Less目的:为了对35584进行安全验证,需要调高后置稳压器LDO_μC的输出电压,然后观察35584是否会对MCU安全关断。
问题:后置稳压器LDO_μC的输出电压是否可以修改,以及通过什么方式可以修改?
Hi!
I use the CCU6 timer in my project, as in the example "CCU6_ADC_1 for KIT_AURIX_TC397_TFT" , but instead of one ADC Group, I use eight. I assigned each one as a master, and for each one I specified "IfxEvadc_TriggerSource_0" (everything is as in the example). Also in the interrupt handler, I measure the time to see the actual sampling rate (the time it takes for the counter to reach the sampling rate value). For one Group at any sampling rate (taking into account that the period of timers T12 and T13 does not exceed 65535), the time takes 1 second (if you just run the code from the example), but if I use two Groups, the time is halved to 0.5 seconds (that is, the frequency is doubled?), if I use four Groups, then by the same analogy, the time is reduced fourfold (to 0.25 seconds) and so on. At the moment, I don't understand the documentation well, and I can't explain this behavior in any way. I need eight Groups (each with one Channel) to convert values at the same time, and I tried to implement this using CCU6. I tried to assign one Group as a master and the others as slave, but the result was only on the Channel of the Master Group.
How to make ADC Groups work synchronously correctly? I don't have a task to use only CCU6, it just seems to be the most convenient for me right now.
I am working with a custom board with an AURIX TC397X chip. At the moment, the eight analog inputs (receiving the signal I'm working with) for the ADC are divided into eight Groups.
Show Less