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AURIX™ Forum Discussions

Translation_Bot
AURIX™
I used the example of SPI_DMA_1_TC297 to make modifications in order to set the QSPI Master to multiple CS pins. CS1 is used to read the control of F... Show More
Translation_Bot
AURIX™
I'm looking for some guidance. I'm currently only tuning send, and the basic configuration and send function is as follows. After calling the transmit... Show More
Ashwini
AURIX™
Hello Infineon, I am working on EDSADC module of Aurix TC3xx series, referring EDSADC_1_KIT_TC397_TFT and EDSADC_1_KIT_TC375_LK example projects to un... Show More
FD_aurix
AURIX™
Hi All We'd like to configure a node of the Aurix to be able to work in passive (no message send/ACK/NACK to avoid error frame on the CAN line in case... Show More
Bertxu
AURIX™
hi: 请问, 1.关于AUTOSAR MCAL  driver 与demo 例程中的Libraries中的driver 有什么不同之处? 2.AUTOSAR MCAL  driver中是否包含了TC397 safty menu中提及的SM(安全机制)的接口? 3.是否有文档介绍AUTOSAR MC... Show More
Translation_Bot
AURIX™
Please tell me that normally the initial value of the variable is placed on PFLASH and put into DSRAM under Ifx_C_Init();, if I want to put the initia... Show More
HossamAlzomor
AURIX™
Hi, Regarding the application note AN238230 , is it possible to generalize the concept and use it for Octa SPI? AN238230 - Quad SPI master emulation using AURIX™ GTM (infineon.com)... Show More
HossamAlzomor
AURIX™
Hi,Where could I find the source code for application note AN238230  titled "Quad SPI master emulation using AURIX™ GTM"  AN238230 - Quad SPI master emulation using AURIX™ GTM (infineon.com)... Show More
Isobel
AURIX™
I have an Infineon evaluation board named TriBoard TC3X7 TH V2.0.The board runs an AUTOSAR OS and I want to trace the runtimes of the system and the r... Show More
john_kas
AURIX™
Hello all. I know that the Aurix ADC offers the functionality synchronize channel conversions between different ADC kernels. However due to some limit... Show More
Forum Information

AURIX™

In this forum you can post your questions, comments and feedback about the 32-bit AURIX™ TriCore™ Microcontroller. The AURIX™ offers the highest scalability in performance, memory & peripherals across application. It is a safe and secure companion chip, meeting both the ISO functional safety standards and EVITA full security standards. Here you can also find the links to the latest board pages, SW and Tools GitHub, trainings, documents and FAQs