Hello Community,
I m working on a Vector FBL on Tc3E7 and i m trying to communicate with an SBC using QSPI4.

I configured the Baudrate to 500000 and the fQSPI to 160Mhz.

I m using Mcal SPI driver.

using the logic analyzer(screenshot below), I saw that the clock is sent out with the correct frequency, the MOSI data is correct, the chipselect is also triggered correctly and there is data returned from SBC in the MISO line.

However, the SPI does not read the data in MISO line and returns FFFFF intead.

Do you have any hints what could be the issue here ?

hello everyone，

         I want to ask a question about OVC of TC397.

Setting Description： 

       I use multicore of TC397.The target adress is in PF4. The OVC redirection address is LMU(0xBxxxxxxx).The Cache(DCache and PCache) of each core is enable in startup. The OVC of each core is enable by core0. and each section is set by core0.DCINVAL is set to 1 by core 0. In a word, every setting about OVC is set by core0.

      Var_A is a const variable in my target adress and redirection adress is  LMU（0xBxxxxxxx),Var_B and Var_C are common variable. I use  XCP to change Var_A in core0, use (Var_B = Var_A) in core0, use (Var_C = Var_A) in core4.     

Error Description:

     Var_B is changed with Var_C,but Var_C is not and keep init value.

       Then I do some test,the result is that the DCache of core4 must be bypass,regardless the Dcache of  Core 0 is enable or bypass,  both Var_B and Var_C can be changed  with var_A. 

But in my project ,I must enable Dcache of each core to improve performance.

What can I do to make  OVC work in the situation of making DCache of each core enable.

thank you