AURIX™ Forum Discussions

Where does the program resume when waking up from Standby mode?

For example, in the following program, will it be restarted from func_TestA?

IfxScuWdt_clearSafetyEndinit(IfxScuWdt_getSafetyWatchdogPassword());
IfxScuWdt_clearCpuEndinit(IfxScuWdt_getCpuWatchdogPassword());
--------------- omit -----------------------
MODULE_SCU.PMCSR[0].B.REQSLP = REQUEST_STANDBY;
IfxScuWdt_setSafetyEndinit(IfxScuWdt_getSafetyWatchdogPassword());
IfxScuWdt_setCpuEndinit(IfxScuWdt_getCpuWatchdogPassword());

func_TestA();
func_TestA();

soft_Reset_func();

Hello,

On a TC37x evaluation board, I am trying to write on the PFLASH1 while executing from the CPU0. I can write without any problem on PFLASH0, but writing on PFLASH1 always results in a Data Asynchronous Error. Is there any way to get it working ? Or it is just not possible ?

Thank you,

Ana

Hi.

I use a lot of AURIX MCU and HSM.

I currently need HSM Reset.

I couldn't find any explanation about HSM Reset in manuals.

How can I only reset HSM (Arm Cortex)?

< I already know HOST Reset, I need to reset only HSM>

Thanks

Best Regards

Phillip

Hi,

I have recently started working with TC387 and have been struggling to understand some points regarding the ‘groups’ in EVADC. I have gone through the user manual and the example projects but did not find anything related to the issue in them.

I am looking for some help in understanding the following behavior:

If any channel of a group is configured as a slave conversion source and I want to use the same group (different channel) for another ADC measurement, then this new input must also be configured as a slave source. If I configure the new input as queueMaster then the adc output for the channel configured as slave, reads 0. The valid flag is always 0 for it.

If I change the conversion source for the new input to slave, then both inputs work as expected.

If you need any additional information, please let me know.

Thanks! 😊

I would like to understand the following : 

The register STCON has access mode as ST, P0. P0 means a master can access it when accen bit is enabled.

1. I have opened the Trace32 and requested a Cold PORST. The execution in Trace32 is now at the start of the bootloader.

2. In this condition, I try to write 0 to this STP bit. But I get SPB bus error meaning the master(CERBERUS) cannot access it. The access enable bit for the master (here CERBERUS) is Enabled in SCU_ACCEN00/10. 

If only SSW can write this bit, Why is then the access mode P0 given ? Is it possible to modify the value to 0 at any point ?

Hello.

I have a question about Aurix Development Studio.

After install the ADS, I can't debug due to debugger IO error.

So I tried to install the DAS64, but I can not install the DAS64 like below.

But I can not found the DAS64 program and folder in my program folder.

How to uninstall and install the DAS64 program. 

Hello, I have some doubts related to Data reduction mode feature of EVADC (32.10.5 Data Modification of Infineon-AURIX_TC3xx_Part2-UserManual-v01_00-EN.pdf). my question exactly how results are being accumulated and what should be expected result after accumulation? can anyone explain the process?