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AURIX™ Forum Discussions

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Anonymous
AURIX™
Hi!I'm currently working on a application that uses the QSPI module on a TC234 micro.Previously we have been calculating the parity bit by our-self, b... Show More
User17142
AURIX™
Hi, I am working on Tricore TC297B and I am interested to know about establishing core to core communication. If any example code or documents availab... Show More
User17059
AURIX™
Hi, We are using Infineon TC-297 Development kit. I am going through the sample code . I got stuck with this part of code. What is the use of the f... Show More
User17092
AURIX™
I find there is (JTAG *) on Tool interface of 7x ED table on https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/tc2xx-emulation-devices/... Show More
User17079
AURIX™
On a new factory erased chip (TC264 BC), would it be possible to write to PFLASH through FlsLoader_Write without executing FlsLoader_Erase?
User16898
AURIX™
hi,I have a hardware interruption in which another hardware interruption is nested. Actually only the first interruption works properly nested one is... Show More
User17041
AURIX™
Hello Guys,i am working as SW-Engineer at an OEM since long time,Inside MCAL Layer I detected a robustness issue, the Fls_lMainRead() inside Fls_17_Dm... Show More
User16898
AURIX™
Hi,I have following question:what happens when the same interrupt occur twice ?I use timer interruption that is handled once per 1ms ( timer interrupt... Show More
User16898
AURIX™
Hi,I,m currently developing project on tc22x. I'm using following modules that uses interruptions :- gtm_tom timer- asclin1_spiOnly hardware interrupt... Show More
User16280
AURIX™
Hi Reader,After loading the data into Tx FIFO(Data entry register 0), i am unable to see the content on debugger. I am skeptical whether the data has ... Show More
Forum Information

AURIX™

In this forum you can post your questions, comments and feedback about the 32-bit AURIX™ TriCore™ Microcontroller. The AURIX™ offers the highest scalability in performance, memory & peripherals across application. It is a safe and secure companion chip, meeting both the ISO functional safety standards and EVITA full security standards. Here you can also find the links to the latest board pages, SW and Tools GitHub, trainings, documents and FAQs