Hi!

I'm currently working on a application that uses the QSPI module on a TC234 micro.

Previously we have been calculating the parity bit by our-self, but right now I want to try out the hardware parity bit calulation instead, to save some CPU load.
This is how it looks on a oscilloscope with my own parity bit calculation:

(I know that the fall/rise curves are soft, but currently I'm not testing against any slave)

This is how it looks when I use the hardware calculated parity bit:


The payload is the same between the pictures, and what I can see is that the payload seems to be shifted to left with one step:
Expected data:
1110010000000001 where the LSB is the parity bit

but with the HW calculated parity bit I get:
1100100000000001

My settings when I use the the HW calculation:
BACON.PARTYP = 0
BACON.BYTE = 0
BACON.DL = 0xE <<-- 15 bits payload + 1 parity bit
ECON.PAREN = 1

Settings when I use my own parity bit calc:
BACON.PARTYP = 0
BACON.BYTE = 0
BACON.DL = 0xF <<-- 16 bits payload
ECON.PAREN = 0


Does anyone know why this is happening when I use the HW calculated parity bit? I can't find anything in the data spec... Show Less

Hi, I am working on Tricore TC297B and I am interested to know about establishing core to core communication. If any example code or documents available please let me know. Show Less

Hi,
We are using Infineon TC-297 Development kit. I am going through the sample code . I got stuck with this part of code. What is the use of the function _mfcr(CPU_CORE_ID) ??? ( where core ID value is 0xFE1C)


static __inline__ __attribute__((__always_inline__))
unsigned _mfcr (const unsigned __regaddr)
{
unsigned __res;
__asm__ volatile ("mfcr %0, LO:%1"
: "=d" (__res) : "i" (__regaddr) : "memory");
return __res;
}


What does this part of code means??? Show Less

I find there is (JTAG *) on Tool interface of 7x ED table on https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/tc2xx-emulation-devices/ .

Is there anything special about JTAG on TC277 ED chip? Does that mean that there is no full JTAG accessing function on TC277 ED chip?

I tried to read memory space of TC277 emulation device but got timing out error through DAS miniwiggler. Except emulation device ram space, all there memory can be accessed by DAS through Miniwiggler. Show Less

hi,
I have a hardware interruption in which another hardware interruption is nested. Actually only the first interruption works properly nested one is not handled.

TriCore™ V1.6 Core Architecture user manual says that,
there are interruptions groups, in the interrupt vector table,
that set the maximum available (in scope of the group) priority to the first interruption occurrence
so no other interrupt will occur before current one is finished.
By default there is one group in whole PiPN range (0-255), so first interrupt is set with priority 255 and block all others.

User manual says it's possible
to create custom groups of interruptions but i couldn't find any reference to it.

how can I create such groups ?

tricore user manual(chapter 5.6.2, page 71) :
https://www.infineon.com/dgdl/tc1_6__architecture_vol1.pdf?fileId=db3a3043372d5cc801373b0f374d5d67 Show Less

Hello Guys,
i am working as SW-Engineer at an OEM since long time,

Inside MCAL Layer I detected a robustness issue, the Fls_lMainRead() inside Fls_17_Dmu.c uses a do {...} while(count>0) loop to copy data from NV to RAM buffer.
if the size (presented in a global struct) is Zero, the copy will overwrite the whole RAM until stopped by exception. Reading 'Zero' Bytes may be wrong, but at the end the value is set to zero,
so a second (unintended) call of the function also leads to this behaviour.
Changing the loop into a while(count>0) { ...} would solve this issue.

If it's my code i would do such immediate, but I received it from my tTier1 Ecu supplier, he received it from his Autosar Stack supplier, that company finally received the code from Infineon.

Teh code has a 'do not modify' attribute, so lawyers and business staff say. do not modify, you will loose the Guarantees. The only allowed to do is Infineon.

I want to have this 'bug' changed before my car is going into production. For that i ask here how to contact MCAL developers/responsibles to supply them the details here.
Going the full chain backwards i am quite shure will be slower or even blocked.

Target CPU is TC39x, using AUTOSAR 4.2 and up.

If ALL is implemented correct, this will not occur, but for ASIL relevant SW i expect also a good kind of ROBUSTNESS against (maybe seldom) parameter faults.

Here the reduced code:

uint32 cnt; // shall be set by other function to a value > 0

uint8 *src, *dst;

void CopyBuffer(void)
{
do
{
*dst++ = *src++;
cnt--;
} while (cnt>0);
}

i could use sint32 cnt to reduce overwriting to ONE byte,
or move the while() up to not copy any byte at all. Show Less

Hi,
I have following question:

what happens when the same interrupt occur twice ?

I use timer interruption that is handled once per 1ms ( timer interrupt). Interruption handler execute some code.
There is possibility, that some parts of code, inside interruption, could execute more than 1ms. What happens if code inside interruption will execute more than 1ms
and next timer interruption,with the same priority, occur ?


used timer module TOM,GTM
developing platform Aurix TC22L , (lockstep not used)
Using only hardware interrupts Show Less

Hi,

I,m currently developing project on tc22x. I'm using following modules that uses interruptions :
- gtm_tom timer
- asclin1_spi
Only hardware interrupts are used.

spi has 3 interrupts: tx, rx, error, with priorities 1, 2, 3
timer has one interrupt with priority 10

Spi, placed in main() loop ,works good.
When i place it in the timmer interrupt it stop working,

the
transfer_in_progres
bit is constantly set to true
and spi do not send/receive anything

I'm enabling interrupts every time the timer interruption execute.

I also use multican module that does not use any interrupts and it works fine in timer interrupt, so I think it's the interruption configuration problem.


why such situation happens despite higher Spi interrupts priorities ? Show Less

Hi Reader,

After loading the data into Tx FIFO(Data entry register 0), i am unable to see the content on debugger. I am skeptical whether the data has been loaded or not. Any suggestions to check this?
However i am considering to check the SPI lines at channel level with a logic analyser.

Spi_Regs->Bacon_Entry_Reg = (0 << 28/*CS*/)|(0 << 21/*MSB*/)|(1 << 0/*LAST*/)|(7 << 23/*DL*/);
uint32 buf = 0xCC;
Spi_Regs->Data_Entry_Reg0 = buf;
uint32 buf_1=0x00;
buf_1 = *(uint32*) 0xF0001D90;

Thanks in advance!!! Show Less