AURIX™ Forum Discussions
Hello,
I am trying to connect Infineon Miniwiggler v3 to the Aurix Tc387, by using Infineon Memtool 2021.8.
But couldn't able to establish the connection between them.
Need support related to Memtool Settings and need details for DAP Miniwiggler v3.
Please support!!
Show LessUnsure which part of the forum i should post to .. i did have this on the hardware side of things but it may be 'finger trouble'
As it stands at the moment i've adapted the example code using other forum uses 'comments'
i now have 2 nodes , 1 transmit , 1 receive , they are in loop back mode the receive has 2 filters set up. If i transmit from the one node with either of the message ID'd set up in the filter the interrupt goes off plus data is received .. awesome we've made a step forward.
if i turn loop back off and have my can tool connected , i can transmit fine but when i send from my can tool the micro does not respond .
with regards the filtering , i'd like to filter a range of id's but seams i cannot
shed any light people ?
I've tried the code on 2 dev kits so i know it me / code and not hardware.
I've notice some examples start setting base memory address and some don't i've tried both ways with using the addressing the board becomes a 'brick' and i receive a 'trap '.
i'm attching my MCMCAN file , i'm new to infineon so i'm hoping it something i'm not setting or doing (i'm used to dspic / Ti micros) .. any help would be grateful
Thanks,
Show LessHi,
In our application, the GETH Rx DMA is suspended (i.e, DMA Channel i Status Register.RBU == 1) because Rx DMA failed to get Rx descriptor.
According to "TC3xx User Manual part2.pdf" page 2921,
"To resume processing Rx descriptors, the application should change the
ownership of the descriptor and issue a Receive Poll Demand command.
If this command is not issued, the Rx process resumes when the next
recognized incoming packet is received. In ring mode, the application
should advance the Receive Descriptor Tail Pointer register of a channel. "
However, we can not find any introduction about "Receive Poll Demand command." in the manual.
So , how to resume from the Rx DMA suspend state?
Is it enough to just clear the RBU bit and re-start the Rx DMA after the application
advanced the Receive Descriptor Tail Pointer register of a channel?
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I wanted to configure the ATOM_TRIG_CHAIN for enabling the Synchronizing register after the ATOM instance [i](ATOM[i+1]).
This Configuration bits are present in CCM[i]_HW_CONF. But as per user manual this register contains mirror values of TOP-LEVEL Register GTM_HW_CONF. This all Register are having Read-Only type of Access.
Is there any other way, where we can configure values for ATOM_TRIG_CHAIN ??
Show LessHI,
There is no problem with SPI communication using SDK program. After configuring SPI using MCAL, SPI can read and write normally when running in DeBug single step, but the data read by SPI is incorrect when running at full speed. I want to know what causes this problem and how to solve it.
Please reply as soon as possible, thank you very much
Show LessHello,
We are working on AURIX TC364 for BLDC motor control project for functional safety level ASIL B (automotive application).
Is it required to have a decoupling capacitor at the reset pin?
I think its recommended to have a capacitor at reset pin, the logic is to prevent noise at reset pin & also to have power on reset.
Can anybody let me know?
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Background: Using TC234 for PWM control of PMSM 3-phase motor. The driver PWM frequency is at 20kHz. The current control SW is run at 10kHz, so the GTM outputs the same pulse-width/duty twice for every controller update.
Problem: At higher motor speed we get a clear 10kHz tone. Reason appears to be that at high speed the reference duty from the controller changes rapidly, and the 2:1 ratio causes a stair-case shape, resulting in this noise.
If we run the controller SW at 20kHz the problem goes away, but this puts too much penalty on CPU load, and is not really necessary. Either of the following options would also work:
a) in the 10kHz controller calculate separate duty reference for the first/second 20kHz pulse. This would add only minor CPU load, but the GTM would need to accept and output two reference values per channel.
b) letting the GTM process the reference duty with a FIR filter or similar, e.g. y=0.5*(x(n)+x(n-1)).
Does anyone know if it’s possible to configure the GTM to support either of these?
Alternatively we’ll need to add a small 20kHz part in the CPU but it would be neater to push this job to the GTM.
Thanks.
Show LessHello all, is there any limitation with respect to TC3x multi core usage vs TC2x Multi core usage?
Example: Does TC3x not allow multi core shared data exchange between codes running from different cores?
Show Less