Hello,

we are using the Aurix tc27x C-step controller for multiple projects. The newer D-step chips have better availability, therefore it would make sense to switch to D-step for new projects. However I could not find information about what changed between CA step and the current DC step. Does anyone has any documentation about the changes between the revisions of the tc27x chips?

Thanks in advance. Show Less

Hello Support,

Can you please tell me the reason and solution for the following SMU alarm?

XBAR0 Bus Error Event -- ALM17[17] in Aurix 2G device.



Best Regards Show Less

Hello Support,

Can you please explain the meaning of this sentence as shown below from OCDS manual from end-user perspective?

"The IOClient
however has the higher priority."

What does IOClient means from User Perspective?
Does the above sentence effectively means External Debugger can over-ride the HARR bit to any desired state even though the Target Software is writing continuously clearing HARR bit to zero?
I am assuming IOClient means external Debugger access to Target.
Please confirm.


Best regards Show Less

Hello Support,
By default, OCDS is disabled for Aurix 2G when Debugger is not connected.
Hence according to the User Manual, for Application Reset, there will also for Debug Reset.
Does this mean during Application Reset when OCDS is disabled, we should also see Bit 19 -- RSTSTAT.CB1=1?

Attached some snippets for reference.


Best Regards Show Less

Hello Support,

In the TC2xx Hardware Design Guide App Note :
https://www.infineon.com/dgdl/Infineon-AP32469_TC2xx_hardware_design_guide-AN-v01_00-EN.pdf?fileId=5546d46269bda8df0169c9ee102823a9

It is mentioned that OCDS should be disabled in the production ECU.
Question is what is the hardware and software design to implement OCDS disable feature is not described.
Can you please elaborate more about this sentence so that we can perform the this task of "OCDS Disable" effectively in the production environment?


Best Regards Show Less

Hello Support,

In Aurix 2G, I want to connect the Debugger Probe physically to the Target ECU for Post-Mortem Debugging and then start the Debugger Application on Host PC to complete the Hot Attach.
I know I can perform Hot Attach the Debugger Application to the Target ECU without any problem for In-Situ debugging activity.
But I want to understand if I can perform Hot-Plugging of the Debugger Probe [MiniWiggler/DAS or iSystem Active/Passive Debug Probe or Lauterbach Trace-32/Debug-POD] and then perform the Hot-Attach of the Debugger.
Please confirm if Hot-Plugging of Debug Probe is possible for Aurix 2G by design.



Best Regards Show Less

Hello,

SW was working fine with the debugger connected. I flashed valid BMHD to let the ECU running without debugger. ECU startup without debugger only one time then when i tried to connect the ECU using the debugger to flash i got " DAP initialization error". The internal WDG is integrated so i expect that SW triggered WDG failures and the ECU is locked. I checked the ESR0 pin but i found that it is connected to pull up resistor so it will be always high. Could anyone help?. Note: HWCFG pins are disconnected and the flashed BMHD was configured to start from internal flash and diasable HWCFG pins.

Thanks Show Less

Hello,

I tried to set BMHD0 and BMHD1 of Aurix TC23x. For this purpose I wrote Lauterbach Trace32 script

; Set BMHD0
Data.Set 0xA0000000++0x17 %Long 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
Data.SUM 0xA0000000++0x17 /Long /ByteSWAP /CRC32
Data.Set 0xA0000018 %Long Data.SUM()
Data.Set 0xA000001C %Long ~Data.SUM()

; Set BMHD1
Data.Set 0xA0020000++0x17 %Long 0xA0080900 0xB3590160 0x00000000 0x00000000 0x00000000 0x00000000
Data.SUM 0xA0020000++0x17 /Long /ByteSWAP /CRC32
Data.Set 0xA0020018 %Long Data.SUM()
Data.Set 0xA002001C %Long ~Data.SUM()

My goal was to clear BMHD0 and set BMHD1 to start executing software from 0xA0080900. Unfortunately after this procedure I have no communication with the CPU.

What's wrong? Can it be undone? Show Less

Hello Support,
In the TC1.6,2 Manual, I found the following sentence :
Figure 19 CSA and Processor SFR Updates on a Context Restore Process

Does the above sentence means all the SFR Registers as mentioned in the Table 109 of Part 1 Aurix 2G User Manual will be updated only on RET and RFE instruction execution, even though CPU writes to these registers?
Please elaborate more about the process of updated SFR Registers of Table 109, especially Bus MPU Protection Registers and ACCEN registers from that table.
What really means from the sentence about SFR update for "Figure 19 CSA and Processor SFR Updates on a Context Restore Process".
Relevant snippets are attached



Best Regards Show Less

HI

I have a Hitex Tantino II debugger which I do not have a problem with, I also have a Lauterbach LA-3500 and a LA-7756 OCDS-Tricore I would like to try and use it again I managed to load elf files few years ago it stopped working I think through grounds being different.
I sent it back and Lauterbach who could not find a problem I thought I would get it out of the cupboard and try again.
I have a start up script adapted from a Easy kit TC1767 but for a TC1782 I just get command locked or
I have tried the following steps
Power LA-3500 with JTAG LA-7756 connected
Power up target
SYStem.CPU TC1782
SYstem.Up get ^ command locked

If I open up Tricore CPU window get
target reset

Tantino II works fine and once I got the Lauterback working although probably with a TC1767 in although mainly just uploading elf files
Carl Show Less