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AURIX™ Forum Discussions

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Anonymous
AURIX™
Hi,after flashing (iROM) the LCDDemo provided by the Free Aurix Entry Toolchain, the TC2X7 V1.0 Application Kit Board is performing an reset within an... Show More
Anonymous
AURIX™
in the define:#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) void __interrupt(prio) __vector_table(vectabNum) isr(void)what is the "vectabNum"? ... Show More
User17612
AURIX™
Hi all, If TESTMODE pin/ball is opened by any accident, the device will go into testmode?Kind regardsLucas #8042000 20412 Show More
User9635
AURIX™
Hello Support,With SSWWAIT=1, there is Foreground Secure Boot feature enabled in HSM.Looks like Host SSW Software will check for HSM2HTF.0 as 1 before... Show More
User19107
AURIX™
Hello,What are the Root causes of SMU3[6] alarm in Aurix TC265D? The clock configurations are proper according to the Errata sheet (5 MHz is selected ... Show More
User19385
AURIX™
Hello all,Does anyone have an example on how to perform Converter Diagnostics on the VADC?How should the Global Test Functions Register be configured ... Show More
User19684
AURIX™
Hello Support Team,-Can you provide me with the type of Evita for this part number TC234LP32F200NACKXUMA1. IS it Full HSM or Medium HSM?-Also can y... Show More
User17612
AURIX™
Hi, I have just received my Application Kit and when I plugged it in the demo code ran correctly. I have just written my 'blinky' code in BIFACES and ... Show More
User19424
AURIX™
HelloI am having trouble reading the A11 Register.I tried: __mfcr(CPU_A11)(&CPU0_A11)->B.ADDR *((unsigned int *)&CPU0_A11)//Also Tried with inline ass... Show More
User9635
AURIX™
Hello Support,Can you please provide me the ARM Revision Number of TRM which is used for HSM Cortex-M3 within Aurix 2G family?I couldn't find any refe... Show More
Forum Information

AURIX™

In this forum you can post your questions, comments and feedback about the 32-bit AURIX™ TriCore™ Microcontroller. The AURIX™ offers the highest scalability in performance, memory & peripherals across application. It is a safe and secure companion chip, meeting both the ISO functional safety standards and EVITA full security standards. Here you can also find the links to the latest board pages, SW and Tools GitHub, trainings, documents and FAQs