AURIX™ Forum Discussions

Hello,

I am working on an Infineon TC397 and I want to do the following:

I want CPU3 to be running on bare-metal which is the default configuration of Infineon TriCore, and all the other CPUs to run Erika OS.

I know the startup flow of the bare-metal application but I am unable to integrate it in Erika, and since CPU0 is running Erika I was thinking of adding the function call of bare-metal to CPU0 to activate CPU3 but I have failed to do it successfully till now.

Does anyone know if this is possible to do? And if yes, how can I integrate the bare-metal startup, which is located in the Infra and iLLD files, to the Erika configuration to start CPU3 on bare-metal instead of the RTOS.

Thank you.

Hi,

Could we get clarification on the below?

1. Due to availability issues, Can we design our system considering the TC397XX256F300SBDKXUMA1 part and later replace it with TC397XX256F300SBDKXUMA2 (without changing the PCB)? Our understanding is both A1 and A2 versions are pin compatible (can use the same footprint and hardware), offer the same functionality and code developed for A1 is directly usable in the A2 part.

             Please let us know if this is fine.

2. What is the difference between A1 and A2?

We don’t seem to have much clarity on the statement below found on the Infineon website. Since both parts have the same SP name (SAK-TC397XX-256F300S BD), there is no change in temperature rating. So, is the ROM code changing? If so, what is the impact on our design?

3. I had a quick glance at the KIT_A2G_TC397_5V_TRB_S manual and I was able to notice the TLF35584QVVS1/2 PMIC chip part in the reference design. Could you please confirm if a PMIC chip is necessary when designing with TC397 MCU? Would there be any implications if we design our system with discrete regulators instead of PMIC?

Kindly let us know your comments.

Hello All, 

I am using TC275 Lite Kit. I am getting SBE (Store Bus Error) / DAE Trap in the below highlighted line.

Attached the images of the Trap window and supporting documents.

#include "Ifx_Types.h"
#include "IfxCpu.h"
#include "IfxScuWdt.h"
#include "IfxQspi_reg.h"
#include "IfxQspi_bf.h"
#include "IfxStm_reg.h"

void Spi_Init(void)
{
/* initialize PORT pins for QSPI0 */
/* initialize I/O function */
P22_IOCR0.B.PC2 = 0x13; /* SLSO P20.13 */
P22_IOCR0.B.PC3 = 0x13; /* SCLK P20.11 */
P22_IOCR0.B.PC0 = 0x13; /* MTSR P20.14 */
P22_IOCR0.B.PC1 = 0x02; /* MRTS P20.12 */

/* Initialize speed grade */
P22_PDR0.B.PD2 = 0x02; /* medium */
P22_PDR0.B.PD3 = 0x01; /* strong, medium edge */
P22_PDR0.B.PD0 = 0x01; /* strong, medium edge */
P22_PDR0.B.PD1 = 0x00; /* default speed grade */

/* Initialize output */
P22_OUT.B.P2 = 0x01;
P22_OUT.B.P3 = 0x01;
P22_OUT.B.P0 = 0x01;
P22_OUT.B.P1 = 0x00;

/* enable QSPI device */
QSPI0_CLC.U = (unsigned long int)0x00000000;

/* set input line selection for MRST pin (PISEL.MRIS) */
QSPI0_PISEL.U = (unsigned long int) 0;

/* Enable Chip Select */
QSPI0_SSOC.U = 0x00040000;

/* set timing characteristics/profile for channel */
QSPI0_ECON2.U = 0x00000844;

/* set up spi device hardware */
QSPI0_GLOBALCON.U = 0x21000000;
QSPI0_GLOBALCON1.U = 0x11050400;

// clear any error flags that might get set during init process
QSPI0_FLAGSCLEAR.U = 0x1ffu;
}

int core0_main(void)
{

uint16 password = IfxScuWdt_getCpuWatchdogPassword();
IfxScuWdt_clearCpuEndinit(password);
Spi_Init();
IfxScuWdt_setCpuEndinit(password);
while(1)
{
}
return (1);
}

Trap Structure :

Trap Table to identify the trap:

DATR register : SBE bit is high.