AURIX™ Forum Discussions
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AURIX™
Before we sacrifice one part and do a cross-section on the part, is there any detailed information on the device substrate anywhere? Are these flip ch...
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Before we sacrifice one part and do a cross-section on the part, is there any detailed information on the device substrate anywhere? Are these flip chip?
Thanks,
Sergeh Show Less
Thanks,
Sergeh Show Less
AURIX™
Hello, Its my first time to work with memory protection concept so excuse my questions if you see them intuitive.1-Once memory protection is enabled t...
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Hello, Its my first time to work with memory protection concept so excuse my questions if you see them intuitive.
1-Once memory protection is enabled this means that all memory is restricted unless i explicitly grant access to a memory region, correct?
2-Should the OS master core system application be granted access rights to all shared memory regions even on the other cores' MPU regions or its not relevant and each core should be the only core getting access to its regions
3-I am using TC37x which is a tricore architecture, I created 6 memory regions as a prototype and granted access to the whole memory address space,first 3 regions are for codes, in the core0 code mpu and gave access to core0 application protection sets, same goes to core1,cor2
second 3rd regions have the same whole address space but for data mpus, just to observe the mpu working, however it didn't I am just stuck at OS_Barrier.c it seems the OS is not happy with my configurations, but the MPU trap bit in DSTR is not raised. so it seems it is not a protection violation but rather something different, any insights?
4-What is the difference between Os system applications and OS applications
Thank you! Show Less
1-Once memory protection is enabled this means that all memory is restricted unless i explicitly grant access to a memory region, correct?
2-Should the OS master core system application be granted access rights to all shared memory regions even on the other cores' MPU regions or its not relevant and each core should be the only core getting access to its regions
3-I am using TC37x which is a tricore architecture, I created 6 memory regions as a prototype and granted access to the whole memory address space,first 3 regions are for codes, in the core0 code mpu and gave access to core0 application protection sets, same goes to core1,cor2
second 3rd regions have the same whole address space but for data mpus, just to observe the mpu working, however it didn't I am just stuck at OS_Barrier.c it seems the OS is not happy with my configurations, but the MPU trap bit in DSTR is not raised. so it seems it is not a protection violation but rather something different, any insights?
4-What is the difference between Os system applications and OS applications
Thank you! Show Less
AURIX™
Hello,I'm developing a bootloader on an Aurix TC297. I'm aware of the two ECC types and how to switch between them. I also understand why traps get ...
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Hello,
I'm developing a bootloader on an Aurix TC297. I'm aware of the two ECC types and how to switch between them. I also understand why traps get generated when reading erased flash while the Safety ECC is enabled.
There are many use cases where the bootloader might attempt to read erased flash, so I need a way to gracefully handle the ECC errors. Is there a recommended solution for this without disabling the Safety ECC? I can't imaging I'm the only one that has run into this problem.
Thanks! Show Less
I'm developing a bootloader on an Aurix TC297. I'm aware of the two ECC types and how to switch between them. I also understand why traps get generated when reading erased flash while the Safety ECC is enabled.
There are many use cases where the bootloader might attempt to read erased flash, so I need a way to gracefully handle the ECC errors. Is there a recommended solution for this without disabling the Safety ECC? I can't imaging I'm the only one that has run into this problem.
Thanks! Show Less
AURIX™
Hi all,I hope Aurix gurus can guide me in the direction to solve my issue with the ASCLIN driver.I have configured the ASCLIN driver (UART) using the ...
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Hi all,
I hope Aurix gurus can guide me in the direction to solve my issue with the ASCLIN driver.
I have configured the ASCLIN driver (UART) using the ILLD driver demo. I am exchanging the data with the sensor (Request - Response).
The transmit from Infineon to the sensor works fine. I am having an issue with the receive packages (RX line).
Issue: I can see on the oscilloscope (RX) that the payload is correct and complete all the time (59 bytes). The problem that I am facing is that the number of bytes I am receiving on the Infineon side is not always complete. I am missing a few bytes sometimes but not always.
I am repeating the same request command a few times in the loop. I found out that the missing bytes are due to the missing RX interrupts. Every time the RX interrupt is triggered I am setting the GPIO pin high and after the execution of interrupt function I am resetting the pin.
This is how I can compare on the oscilloscope the received bytes from the sensor and the triggered RX interrupts. The oscilloscope decodes the sensor received package (59 bytes) correctly all the time. I have also checked the voltage level of the received signals.
So it looks like from the hardware point of view there is no problem.
I understand the RX interrupt happens when the byte comes into the RX-FIFO. So my assumption is that some missing bytes are either discarded by the ASCLIN driver to come into the FIFO or something blocks it. I have checked the FIFO level when the RX interrupt is happened. It corresponds to the INTLEVEL,
which is "1" configured. So every time 1 byte is placed into the FIFO the RX interrupt happens and takes the byte out of the FIFO and packs it into the different buffer. I have also checked the Interrupt priorities. Looks fine to me.
So I was wondering where else I should be looking for a problem? Any ideas what could be the reason that the received bytes seen on the oscilloscope RX line are not fully coming into the RX-FIFO? Is there any way to check whether the bytes have been discarded by the ASCLIN driver or not? Show Less
I hope Aurix gurus can guide me in the direction to solve my issue with the ASCLIN driver.
I have configured the ASCLIN driver (UART) using the ILLD driver demo. I am exchanging the data with the sensor (Request - Response).
The transmit from Infineon to the sensor works fine. I am having an issue with the receive packages (RX line).
Issue: I can see on the oscilloscope (RX) that the payload is correct and complete all the time (59 bytes). The problem that I am facing is that the number of bytes I am receiving on the Infineon side is not always complete. I am missing a few bytes sometimes but not always.
I am repeating the same request command a few times in the loop. I found out that the missing bytes are due to the missing RX interrupts. Every time the RX interrupt is triggered I am setting the GPIO pin high and after the execution of interrupt function I am resetting the pin.
This is how I can compare on the oscilloscope the received bytes from the sensor and the triggered RX interrupts. The oscilloscope decodes the sensor received package (59 bytes) correctly all the time. I have also checked the voltage level of the received signals.
So it looks like from the hardware point of view there is no problem.
I understand the RX interrupt happens when the byte comes into the RX-FIFO. So my assumption is that some missing bytes are either discarded by the ASCLIN driver to come into the FIFO or something blocks it. I have checked the FIFO level when the RX interrupt is happened. It corresponds to the INTLEVEL,
which is "1" configured. So every time 1 byte is placed into the FIFO the RX interrupt happens and takes the byte out of the FIFO and packs it into the different buffer. I have also checked the Interrupt priorities. Looks fine to me.
So I was wondering where else I should be looking for a problem? Any ideas what could be the reason that the received bytes seen on the oscilloscope RX line are not fully coming into the RX-FIFO? Is there any way to check whether the bytes have been discarded by the ASCLIN driver or not? Show Less
AURIX™
Hi,I have a KIT AURIX TC223 TRB and I'm trying to generate a PWM signal on pin 12 of port 11 but I can't. I've used an example that I found on iLLD do...
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Hi,
I have a KIT AURIX TC223 TRB and I'm trying to generate a PWM signal on pin 12 of port 11 but I can't. I've used an example that I found on iLLD documentation. The example is the following:
Could you explain me what is wrong?
Thank you in advance. Show Less
I have a KIT AURIX TC223 TRB and I'm trying to generate a PWM signal on pin 12 of port 11 but I can't. I've used an example that I found on iLLD documentation. The example is the following:
#include
#include "IfxCpu_Irq.h"
Ifx_GTM *gtm = &MODULE_GTM;
#define TOM0_CH0_PRIO 10
float32 frequency;
IFX_INTERRUPT(TOM0Ch0_ISR, 0, TOM0_CH0_PRIO)
{}
int core0_main(void){
/*
* !!WATCHDOG0 AND SAFETY WATCHDOG ARE DISABLED HERE!!
* Enable the watchdog in the demo if it is required and also service the watchdog periodically
* */
IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword());
// install interrupt handlers
IfxCpu_Irq_installInterruptHandler (TOM0Ch0_ISR, TOM0_CH0_PRIO);
// enable GTM clock
frequency = IfxGtm_Cmu_getModuleFrequency(gtm);
// Enables the GTM
IfxGtm_enable(gtm);
// Set the global clock frequency to the max
IfxGtm_Cmu_setGclkFrequency(gtm, frequency);
// Set the CMU CLK0
IfxGtm_Cmu_setClkFrequency(gtm, IfxGtm_Cmu_Clk_0, frequency);
// FXCLK: used by TOM and CLK0: used by ATOM
IfxGtm_Cmu_enableClocks(gtm, IFXGTM_CMU_CLKEN_FXCLK); //Here was IFXGTM_CMU_CLKEN_FXCLK | IFXGTM_CMU_CLKEN_CLK0
// initialise TOM
IfxGtm_Tom_Pwm_Config tomConfig;
IfxGtm_Tom_Pwm_Driver tomHandle;
IfxGtm_Tom_Pwm_initConfig(&tomConfig, gtm);
tomConfig.tomChannel = IfxGtm_Tom_Ch_7; //Here was IfxGtm_Tom_Ch_0
tomConfig.period = 20;
tomConfig.dutyCycle = 10;
tomConfig.interrupt.ccu0Enabled = FALSE;
tomConfig.interrupt.isrPriority = TOM0_CH0_PRIO;
tomConfig.pin.outputPin = &IfxGtm_TOM0_7_TOUT101_P11_12_OUT; //Here was IfxGtm_TOM0_0_TOUT106_P10_4_OUT
IfxGtm_Tom_Pwm_init(&tomHandle, &tomConfig);
while (1)
{
}
return 0;
}
Could you explain me what is wrong?
Thank you in advance. Show Less
AURIX™
Hello All, Are we allowed to use GTM (TIM and TOM) sub-modules using Hightec Free Entry Tool chain and pls debugger environment evaluation version ...
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Hello All,
Are we allowed to use GTM (TIM and TOM) sub-modules using Hightec Free Entry Tool chain and pls debugger environment evaluation version and using Triboard TC277.
I tried to use the TIM channel to measure the PWM signal using the Hightec(Free Entry toolchain) but it did not work in the "TC277 Triboard".
But the same code worked with "Aurix Development Studio" using TC277 "Application Kit".
Please can anyone shed your thoughts on why the GTM not working in Triboard using Hightec IDE?
Many Thanks to you people. Show Less
Are we allowed to use GTM (TIM and TOM) sub-modules using Hightec Free Entry Tool chain and pls debugger environment evaluation version and using Triboard TC277.
I tried to use the TIM channel to measure the PWM signal using the Hightec(Free Entry toolchain) but it did not work in the "TC277 Triboard".
But the same code worked with "Aurix Development Studio" using TC277 "Application Kit".
Please can anyone shed your thoughts on why the GTM not working in Triboard using Hightec IDE?
Many Thanks to you people. Show Less
AURIX™
Hi
How can I place of special group of variable in a determined part of memory?
How can I place of special group of variable in a determined part of memory?
AURIX™
Hi
is it possible to enter specific core into standby mode or IDLE mode on the TC399.
if so, then how?
is it possible to enter specific core into standby mode or IDLE mode on the TC399.
if so, then how?
AURIX™
Hi,What is a good, simple, inexpensive debug / flash program solution? There seem to be a lot of choices out there. I will be using it on a TC375 with...
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Hi,
What is a good, simple, inexpensive debug / flash program solution? There seem to be a lot of choices out there. I will be using it on a TC375 with a custom board.
Ideally, it would work within the Aurix Development Studio.
Thank you,
Charlie Show Less
What is a good, simple, inexpensive debug / flash program solution? There seem to be a lot of choices out there. I will be using it on a TC375 with a custom board.
Ideally, it would work within the Aurix Development Studio.
Thank you,
Charlie Show Less
AURIX™
Hi everybody,
is there something like a unique chip identifier for Tricore TC267 processor?
Thanks
is there something like a unique chip identifier for Tricore TC267 processor?
Thanks
Forum Information
AURIX™
In this forum you can post your questions, comments and feedback about the 32-bit AURIX™ TriCore™ Microcontroller. The AURIX™ offers the highest scalability in performance, memory & peripherals across application. It is a safe and secure companion chip, meeting both the ISO functional safety standards and EVITA full security standards. Here you can also find the links to the latest board pages, SW and Tools GitHub, trainings, documents and FAQs
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