AURIX™ Forum Discussions

Hi All,

I applied in mid July for permission to view the HSM documents and code-base but I'm being told it'll take till end of August to get the NDA handled with my university. The hold up is entirely on the part of Infineon. Does this seem normal?

Thanks.

Hello all,

I have a requirement to read the DSADC alternate PIN for each trigger from GTM.

An ISR is created from the same triggering source to update the alternate channel, but i couldn't see the channel update in register. I have attached code details below.

Am i missed any channel related configuration ?

IFX_INTERRUPT_WITH_ENABLE(intr_name, CPU3, ISR_PRIORITY)  

{

if(DSADC_Dynamic_Cfg == 1U)         //static variable
{
DSADC_Dynamic_Cfg = 0U;

MODULE_EDSADC.CH[5].MODCFG.B.INSEL = (uint32)DSADC_INPUTPIN_POSITIONB;
MODULE_EDSADC.CH[5].MODCFG.B.INMODE = (uint32)DSADC_SOFTWARE_CONTROL;
MODULE_EDSADC.CH[5].MODCFG.B.INMAC = (uint32)DSADC_SINGLE_STEP_MODE;
MODULE_EDSADC.CH[5].MODCFG.B.INCWC = (uint32)1U;

}
else
{
DSADC_Dynamic_Cfg = 1U;

MODULE_EDSADC.CH[5].MODCFG.B.INSEL = (uint32)DSADC_INPUTPIN_POSITIONA;
MODULE_EDSADC.CH[5].MODCFG.B.INMODE = (uint32)DSADC_SOFTWARE_CONTROL;
MODULE_EDSADC.CH[5].MODCFG.B.INMAC = (uint32)DSADC_SINGLE_STEP_MODE;
MODULE_EDSADC.CH[5].MODCFG.B.INCWC = (uint32)1U;

}

}

Hi, all

I am working with MCMCAN_1_KIT_TC397_TFT sample code.

I connected the Tx/Rx pin on TC397 to a TLE9255W CAN transceiver outputting the CANH/L signal on my CAN bus.

The pin is defined as below,

/*******************************************************************************************/

IfxCan_Can_initNodeConfig(&g_mcmcan.canNodeConfig, &g_mcmcan.canModule);

g_mcmcan.canNodeConfig.busLoopbackEnabled = FALSE;
g_mcmcan.canNodeConfig.nodeId = IfxCan_NodeId_0;

g_mcmcan.canNodeConfig.frame.type = IfxCan_FrameType_transmit;
g_mcmcan.canNodeConfig.interruptConfig.transmissionCompletedEnabled = TRUE;
g_mcmcan.canNodeConfig.interruptConfig.traco.priority = ISR_PRIORITY_CAN_TX;
g_mcmcan.canNodeConfig.interruptConfig.traco.interruptLine = IfxCan_InterruptLine_0;
g_mcmcan.canNodeConfig.frame.mode = IfxCan_FrameMode_fdLongAndFast;
g_mcmcan.canNodeConfig.interruptConfig.traco.typeOfService = IfxSrc_Tos_cpu0;
g_mcmcan.canNodeConfig.txConfig.txMode = IfxCan_TxMode_dedicatedBuffers;
g_mcmcan.canNodeConfig.txConfig.txBufferDataFieldSize = IfxCan_DataFieldSize_64;
const IfxCan_Can_Pins pins =
{
&IfxCan_TXD00_P34_1_OUT, IfxPort_OutputMode_pushPull,
&IfxCan_RXD00G_P34_2_IN, IfxPort_InputMode_noPullDevice,
IfxPort_PadDriver_cmosAutomotiveSpeed2
};
g_mcmcan.canNodeConfig.pins = &pins;
IfxCan_Can_initNode(&g_mcmcan.canSrcNode, &g_mcmcan.canNodeConfig);

/*******************************************************************************************/

The output waveform as shown below

(Red: CANH Yellow: CANL Blue: Tx from TC397)

The waveform of the CAN bus was not fit to the protocol.

However, after decreased the baudrate setting of CAN as below,

/*******************************************************************************************/

void IfxCan_Can_initNodeConfig(IfxCan_Can_NodeConfig *config, IfxCan_Can *can)

{

    const IfxCan_Can_NodeConfig defaultConfig = {

        .can         = NULL_PTR,

        .nodeId      = IfxCan_NodeId_0,

        .clockSource = IfxCan_ClockSource_both,

        .frame       = {

            .type = IfxCan_FrameType_receive,

            .mode = IfxCan_FrameMode_standard

        },

        .baudRate                                    = {

            .baudrate      = 50000,       //500000 -> 50000

            .samplePoint   = 8000,

            .syncJumpWidth = 3,

            .prescaler     = 0,

            .timeSegment1  = 3,

            .timeSegment2  = 10

        },

/*******************************************************************************************/

(Red: CANH Yellow: CANL Green: Tx from TC397)

I found out that the output waveform was totally correct with my data setting, but the baudrate is limited about 100 kbit/s.

I want to know that how to transmit the CAN data over 500 kbit/s

Thanks for answering!!!

We are trying to create BSW_Code section in DSRAM0 using linker script. 

Lcf_Tasking_Tricore_Tc.lsl:

#define LCF_BSW_SIZE 1k

#define LCF_BSW_OFFSET (LCF_HEAP0_OFFSET - LCF_BSW_SIZE)

section_setup :vtc:linear
{
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
stack "BSW_Code" (min_size = 1k, fixed, align = 8);
}

group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_BSW_OFFSET])
reserved "bsw_tc0" (size = LCF_BSW_SIZE);
"__BSW":= "_lc_ub_bsw_tc0";
"__BSW_END":= "_lc_ue_bsw_tc0";

Map file generated with "bsw_tc0" for 1kb.

|mpe:dsram0 | | bsw_tc0 (4602) | 0x00000400 | 0x7002a200 | 0x0002a200 | 0x00000040 |
| mpe:dsram0 | | heap (4593) | 0x00000800 | 0x7002a600 | 0x0002a600 | 0x00000008 |
| mpe:dsram0 | | ustack_tc0 (4590) | 0x00000800 | 0x7002ae00 | 0x0002ae00 | 0x00000008 |
| mpe:dsram0 | | istack_tc0 (4591) | 0x00000400 | 0x7002b700 | 0x0002b700 | 0x00000008 |

How to declare variable in bsw_tc0 section?

Hi All,

I am able to build the Biface project with Tasking as compiler.

The generated file in "_Out" folder is in hex.

Is it possible to generate  srec (.s19) instead?

Thank you.

Hello. I have found example with FreeRTOS + TC275 but in the example shedular was started only on one of three cores. Shoudn't it be started on all cores? If yes, does something changes in configuration file of FreeRTOS?

Hi!
Today I'm coding on UCBs for MCU tc397, but I don't understand this error code -  ltc E112: cannot locate 1 section(s)
Here's the details:
ltc E112: cannot locate 1 section(s):
ltc I455: requirement: 0x1fc bytes of ROM area in space mpe:vtc:linear
ltc I456: section type: absolute restriction - at address 0xaf400000
ltc I457:  .rodata.UCB_BMHD.BMHD0_ORIG (2) (0x200 bytes)