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AURIX™ Forum Discussions

AURIX™ Forum Discussions

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cha1pi
AURIX™
While trying to flash my TC397 kit , I get this every time. Is there some setting I need to change "::Loading HEX file .......... :⚠️ The given progra... Show More
User18757
AURIX™
Hi,I'm looking for a way to view and extract the content of an uninitialized RAM section of an 3xx cpu.Is the only way to rewrite the UCB with new RAM... Show More
Zeidan
AURIX™
Hallo Everyone, I am implementing I2c Protocol using Aurix TriBoard with tc357 mounted on it based on the LLD example code. I was successfully able to... Show More
saritha
AURIX™
Hello Team, I am new to TC23xx family. can you please provide a information on how to enable HSM and how this can be handled at host side.  any exampl... Show More
VasantharajE
AURIX™
ELF File generation with TASKING Compiler Hello, I am working on tc27x Project using TASKING Compiler. Could you help me please generate the .elf file... Show More
user31000
AURIX™
Hi, I have a question about Safety Flips flops SMU. According to Aurix TC3xx Safety Manual ,The test ESM[SW]:SMU:REG_MONITOR_TEST must be performed in... Show More
YogeshK
AURIX™
Hello Community, If u r reading this thanks for your time. I Have below issue case: Case: In RSTSTAT register EVR33 bit is getting SET sporadically af... Show More
AssafREE
AURIX™
hi all im trying to read SBUS signals from frsky R8 Pro receiver.it defined OK, and i can read correct data using logic analyzer. the thing is that th... Show More
User19698
AURIX™
Hello,I would like to know the status of RSTSTAT register in case of reset triggered after the completion of LBIST. In my opinion, bits which indicate... Show More
User21797
AURIX™
Hi there, Can HW parity check be used in master mode? From iLLD u can config a master ch to use parity check (<IfxQspi_SpiMaster_ChannelConfig>.parity... Show More
Forum Information

AURIX™

In this forum you can post your questions, comments and feedback about the 32-bit AURIX™ TriCore™ Microcontroller. The AURIX™ offers the highest scalability in performance, memory & peripherals across application. It is a safe and secure companion chip, meeting both the ISO functional safety standards and EVITA full security standards. Here you can also find the links to the latest board pages, SW and Tools GitHub, trainings, documents and FAQs