AURIX™ Forum Discussions
While trying to flash my TC397 kit , I get this every time. Is there some setting I need to change
"::Loading HEX file ..........
:⚠️ The given program file is trying to write on reserved memory addresses, which will be skipped."
I'm looking for a way to view and extract the content of an uninitialized RAM section of an 3xx cpu.
Is the only way to rewrite the UCB with new RAMINSEL values?
And what would be the proper way to do this and what are the pittfalls?
Marcus Show Less
I am implementing I2c Protocol using Aurix TriBoard with tc357 mounted on it based on the LLD example code. I was successfully able to communicate with the EEPROM mounted on the TriBoard using I2c. But, i have a problem when I try to communicate with an external slave. The external device always replies with the same value for any register read request I send. When I try to monitor the signals using oscilloscope I can see that the first write is sent where "an unexpected Ack occurs" and then it is re-transmitted again and then the response is received which is always the same response regardless of the register value i try to read. Does any one had a similar problem or might know what would cause such a problem ?
Thanks in advance,
I am new to TC23xx family. can you please provide a information on how to enable HSM and how this can be handled at host side. any example code or application note configure the UCB.
Thank you in advance
ELF File generation with TASKING Compiler
I am working on tc27x Project using TASKING Compiler. Could you help me please generate the .elf file using Cmake .
Kindly share Command for generate .elf file.
I have a question about Safety Flips flops SMU.
According to Aurix TC3xx Safety Manual ,The test ESM[SW]:SMU:REG_MONITOR_TEST must be performed in Start-up phase.
My question Is:
Is it recommended to perform also this test in run time, in a cyclic task , every X ms ?
After SMU activation and lock, all SMU registers are write protected to prevent unwanted modifications during runtime. But the SFF test for SMU requires to write the SMU registers to activate/run a SFF test.. It would be needed to unlock the SMU temporarily to run a SFF test or to leave the SMU unlocked to allow these tests...Show Less
If u r reading this thanks for your time.
I Have below issue case:
Case: In RSTSTAT register EVR33 bit is getting SET sporadically after the Warm Reset ?
- Already known things: EVR is regulator which is supplies the PFLASH. In case of the under-voltage or Over-voltage detection this bit is expected to getting set. under-voltage or Over-voltage detection can be done by using the SCU_EVRSTAT register, but in my case there no UVO or OV flag is SET.
Does anybody having the any suggestion, how to debug it further ?
Any idea, hint or clue is appreciated 😊
im trying to read SBUS signals from frsky R8 Pro receiver.
it defined OK, and i can read correct data using logic analyzer.
the thing is that the RX signal is inverted and i dont have any HW inverter on board.
can i invert the signal in software? i mean can i configure the channel to expect an inverted signal?
or is it a way to use i/o monitor to invert the signal?
I would like to know the status of RSTSTAT register in case of reset triggered after the completion of LBIST. In my opinion, bits which indicates COLD reset should get set in case of LBIST reset. Show Less
Can HW parity check be used in master mode? From iLLD u can config a master ch to use parity check (<IfxQspi_SpiMaster_ChannelConfig>.parityCheck). But from manual the chapter ch20.8.3 'Parity' is under ch.20.8 'Slave Mode', implying it only work in slave mode.
So if I turn on parity check in master mode (<IfxQspi_SpiMaster_ChannelConfig>.parityCheck = TRUE), will it work?
I am working on TC234.
Thanks for reading, any reply is appreciatedShow Less