AURIX™ Forum Discussions
Hello, I am working on TC399 - ASCLIN module.
Need help/clarification about CE (Collision Detection Error) flag. [User manual part 2, v2.0.0, p36-75]
What my understanding is, collision occurs when more than one LIN slaves tries to respond to same frame on the LIN bus.
Is my understanding is correct?
Can anyone elaborate the part of description in user manual for CE flag. "When transmitting, signals if the transmitted data differs from the received data." ?
Thank you.
I am trying to perform the RAM test for TC233_LP controller for CPU0DSPR by using the example code of MTU_MBIST_1_KIT_TC297_TFT example code. But I am facing the Trap issue, I have attached the trap details and where i am facing the trap issue. I have called RAM test function in cpu0_main. Kindly help me to resolve the issue.
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Hello,
I am working on TC399 LIN module.
Not able to set the ASCLIN0 module to Fast clock.
Observation:
- the CSR.CON bit doesn't get set by hardware.
- the hardware may be taking some more time to set CSR.CON bit.
I am referring Infineon TC39x user manual part 2, v2.0.0, section - 36.3.7.2
Q. What is the fA frequency for fast clock ?
Show Lesshi,
从demo code 和user menu中看到TC397 MCU 从standby 状态下唤醒方式有以下8个,有如下问题:
1.是否支持CAN 信号唤醒(从standby状态下)?
2.设置为IfxPmsPm_WakeupOn_pinA 或IfxPmsPm_WakeupOn_pinB后,是否只能通过UART 发送数据唤醒?
typedef enum
{
IfxPmsPm_WakeupOn_esr0 = 0, /**< \brief ESR0 Wake-up enable from Standby */
IfxPmsPm_WakeupOn_esr1 = 1, /**< \brief ESR1 Wake-up enable from Standby */
IfxPmsPm_WakeupOn_pinA = 2, /**< \brief PINA Wake-up enable from Standby */
IfxPmsPm_WakeupOn_pinB = 3, /**< \brief PINB Wake-up enable from Standby */
IfxPmsPm_WakeupOn_porst = 4, /**< \brief PORST Wake-up enable from Standby */
IfxPmsPm_WakeupOn_timer = 5, /**< \brief WUT Wake-up enable from Standby */
IfxPmsPm_WakeupOn_power = 6, /**< \brief Power Wake-up enable Standby */
IfxPmsPm_WakeupOn_scr = 7 /**< \brief SCR Wake-up enable from Standby */
} IfxPmsPm_WakeupOn;
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Our evaluation board is the TC377_SEC_GTW.
We tried to erase Pflash data, but it took 194 milliseconds to erase the operation, even if it was just one or a few sectors, and it stopped or paused all other processes for that period.
Since the Pflash erase operation is within the control of the Flash Controller, can I find out why the CPU is pausing for 194 ms during this operation?
Can you tell me why it's taking 194 ms and how the CPU determines that it must wait and pause all other processes while performing the erase PFlash operation?
We estimated the erase operation's time, which is 194 ms, and displayed it in the picture below.
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Dear Team,
Is there any source code for CANFD without any Loop-Back Mode condition??
And is there any PIN Layout information for CAN Connector for TC377_SEC_GTW board.
With Regards,
Y.V.Akhil
Show LessHi all,
I have some problems with CAN RX Interrupt Handler function in TC234 Aurix Tricore.
Based on the sample ISR function in CAN example from AURIX, "IfxMultican_Can_MsgObj_readMessage" function is called and return status of Received CAN Message. The problem occurs when I configure like below:
+ In initMultican() function, when initializing the DstMsgObj:
- I configure 2 MsgObjID instead of one as in orginial example, particularly:
Configure: MsgObjID 1 with MsgID = 0x778
Configure: MsgObjID 2 with MsgID = 0x779
+ Using an external software to send CAN message with ID 0x778 and 0x779:
- Both messages trigger RX-ISR Function, however:
readStatus = "IfxMultican_Status_receiveEmpty" when receiving MsgID 0x778
readStatus = "IfxMultican_Status_newData" when receiving MsgID 0x779
After investigating a bit, I found out that the function "IfxMultican_Can_MsgObj_readMessage" using parameter g_multican.canDstMsgObj" which currently stores the status of MsgObjID 2. Therefore, only the CAN MsgID belongs to MsgObjID 2 triggers [NEWDAT] bit in CAN Status register CAN_MOSTATw.
Alternatively, I modify a bit in the RX-ISR function (see the attached figure). In this case, I only searching for the first 10 MsgObjId. My question is that is there another way to immediately help the AURIX controller knows exactly which MsgObjId causing Interrupt? I think my current solution is too ineffective.
I have also attached my MUTICAN.c source file for more detailed information.
I hope that I've stated the problem clearly and be looking forward to hearing from you soon.
Show LessHi All ,
We have bought the KIT_A2G_TC377_SEC_GTW, where we can find the Datasheet, Sample Source code, Schematic and other resources required start the work.
Thanks
BA NAIDU
Show LessHi team,
We are working with AURIX TC397x. We implemented CAN external loopback and can successfully able to transfer and receive CAN messages using CAN0 and CAN1.
We want to make it as CAN FD for that both nominal and data bit registers are feeding with correct bit timing parameters(auto calculation is enabled). And to enable CAN FD, CCCR.FDOE and CCCR.BRSE is being set. But still it is behaving as classical CAN, no switching of baud rate is observed.
Are we missing anything to enable CAN FD?
Why it is falling back to classical CAN even though we configured as CAN FD?
Help is most appreciated.
Regards,
Shafi.
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